antmicro/fastvdma

This system is a configurable DMA controller implemented in Chisel, designed to facilitate data transfers between memory and streams using various bus interfaces such as AXI, Wishbone, and Pipelined Wishbone. It supports 64-bit addressing and allows for dynamic configuration of bus types and data widths through a unified abstraction layer. The project includes a comprehensive test suite using chiseltest to verify memory-to-memory and stream-to-memory operations, along with updated test infrastructure for accurate hardware simulation.

The DMA controller has been refactored to support configurable bus types (AXI4, AXI-Stream, Wishbone) and data widths via a new DMAConfig mechanism, replacing hardcoded constants. This change introduces a unified BusIf abstraction, allowing the system to dynamically select reader, writer, and control bus implementations based on configuration. Additionally, the license has been updated from MIT to Apache-2.0, and the driver now supports loading custom configurations from JSON files.

src/main · high confidence

The DMA controller now supports a wider range of bus interconnect topologies, explicitly adding Pipelined Wishbone (PWB) master configurations alongside existing AXI, AXI-Lite, Wishbone, and AXI-Stream options. Additionally, new Control Status Registers (CSRs) for the high half of the reader and writer start addresses have been defined, enabling access to full 64-bit addressing capabilities.

repository · high confidence

Migrate DMAController tests to chiseltest and add memory-to-memory/stream-to-memory test coverage; Test infrastructure updates: license change, base address support, and AXI read fixes.

The build system has been upgraded to use Chisel version 6.2.0, replacing the previous chisel3 dependency, and migrated to chiseltest 6.0 for testing, removing the legacy iotesters dependency. The project also updates the default Java target to version 17, switches the default Scala version to 2.13.12, and adds the required chisel-plugin compiler plugin. Additionally, documentation dependencies are pinned to Sphinx 7.4.7.

(dependencies) · high confidence

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

• First survey — no prior run to compare against. CAI 58.

• Code Health 100
• Architecture 100
• Maturity 37
• Readiness 55
• Security 100

• 95 commits — 85 feature/other, 10 fixes

• (root) — 30 commits
• src/main — 30 commits
• src/test — 12 commits
• (repo) — 10 commits
• .github/workflows — 6 commits
• .github/scripts — 3 commits
• doc/csr.md — 1 commit
• docs/RegisterMap.md — 1 commit
• docs/requirements.txt — 1 commit
• project/build.properties — 1 commit

• fix: Fix github actions
• fix: Fix test targets in Makefile
• fix: Merge pull request #11 from piotr-binkowski/axi-csr-bus-fix
• fix: Merge pull request #16 from piotr-binkowski/bfm-read-fix
• fix: Merge pull request #8 from piotr-binkowski/wishbone-fix
• fix: [#92037] Fix fail on unset TAG
• fix: [#92037] Fix running indivisual tests
• fix: [FIX] DMA configuration map - missing PWB
• fix: frontend: wishbone-csr: fix too late ack and wrong address range select
• fix: test: Fix reads in AXILite BFM
• change: Add CI
• change: Add ComponentSpec to CI
• change: Add FastVDMA docs
• change: Add Logger
• change: Add configuration register
• change: Add copyright note to readme
• change: Add github action
• change: Add info about the linux driver for fastvdma
• change: Add memory to memory test
• change: Add read interface to AXI4 with simulated memory
• …and 75 more

• 0 containers · 1 bounded contexts · 0 dependency edges (baseline)

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

antmicro/fastvdma was measured the same way every project in this corpus was: the same rubric, at a pinned commit, with the result published in full. Point a surveyor at a repository you know and see whether you agree with it.