chipsalliance/chisel

This system is the Chisel hardware construction language, a Scala-based DSL for describing digital hardware and generating Verilog. It provides a comprehensive library for defining hardware modules, managing hierarchical instantiation, and handling complex data structures like bundles and vectors. The system includes robust simulation and verification capabilities, supporting both direct simulation via ChiselSim and integration with external SystemVerilog simulators. It also features advanced tooling for debug introspection, property-based verification, and configuration-driven design variants, all built on a modernized build infrastructure supporting Scala 2 and 3.

40 changes.

This period focused on migrating the build infrastructure to Mill and integrating the CIRCT-based compilation backend as the primary target for Verilog and FIRRTL emission. It introduced a comprehensive suite of experimental APIs, including hierarchical module instantiation, structured data views, and explicit connectable operators, to modernize hardware design patterns. The work was supported by extensive test coverage and internal refactoring of the stage execution pipeline to ensure stability and extensibility.

41 changes.

This period focused on preparing for the Chisel 7.0.0 release by deprecating legacy FIRRTL package APIs and migrating the build system to Mill. It also introduced significant new features, including the svsim low-level simulation library, a new Property system for non-hardware data, and updated CIRCT intrinsic wrappers, alongside a major migration of the documentation website to Docusaurus 3.

50 changes.

This period focused on migrating the Chisel codebase to support Scala 3, introducing Scala 3-specific macro implementations for core interfaces, utilities, and the compiler plugin while maintaining Scala 2 compatibility. The build system was modernized by migrating core modules, tests, and utilities to Mill, enabling cross-compilation and improved test infrastructure. Concurrently, new features such as the Domain API, ModuleChoice, and ChiselSim simulation framework were introduced to enhance hardware description capabilities and testing workflows.

11 changes.

This period focused on preparing the codebase for Scala 3 by isolating Scala 2-specific macro and API implementations into version-specific interfaces. It also introduced a compatibility layer for ChiselTest to ensure smooth migration, while adding experimental debug intrinsics and constructor parameter reflection to improve hardware introspection capabilities.

The \chisel3.util\ package now includes new hardware modules for arbitration: \Arbiter\ (priority-based), \RRArbiter\ (round-robin), and \LockingRRArbiter\ (round-robin with locking support), along with the \ArbiterIO\ bundle. Additionally, the \BlackBoxUtils\ and \ExtModuleUtils\ packages introduce deprecated traits (\HasBlackBoxResource\, \HasBlackBoxInline\, \HasBlackBoxPath\, and their \ExtModule\ equivalents) to facilitate migration from \BlackBox\ to \ExtModule\, as these capabilities are now native to \ExtModule\.

src/main/scala/chisel3/util · high confidence

The project introduces a new benchmarking module built with the Mill build tool and JMH. This includes a \package.mill\ definition that configures the Scala and JMH versions and depends on the main Chisel library, along with a sample \Benchmark.scala\ file demonstrating how to write and run JMH benchmarks (e.g., \./mill benchmark.runJmh\) to measure performance of Chisel components like \BitPat\.

benchmark · high confidence

The debug module now includes platform-specific implementations to reflect constructor parameters, enabling the collection of debug metadata. This change introduces \CtorParamsPlatform\ for both Scala 2 and Scala 3, allowing the system to extract parameter names and types from object constructors. The Scala 3 implementation includes logic to handle cases with multiple constructors or synthetic parameter names, providing warnings when parameter name retention is insufficient for useful debug output.

core/src/main/scala-2/chisel3/debug, core/src/main/scala-3/chisel3/debug · high confidence

A new compatibility layer in the chiseltest package allows existing ChiselTest-style tests to run on Chisel 7 by wrapping the new ChiselSim simulator. This includes a ChiselScalatestTester trait that provides the familiar test() API with optional automatic reset (disabled by default, configurable via autoResetEnabled and resetCycles) and VCD waveform generation support via WriteVcdAnnotation. The layer also provides implicit conversions for poke/peek/expect operations on Data types and helper methods for Decoupled interface testing, enabling a drop-in migration path from Chisel 6 without requiring test code modifications.

src/main/scala/chiseltest · high confidence

Documentation generation now supports a custom mdoc modifier that renders Chisel-generated Verilog code blocks. This change introduces a new PostModifier service that processes code snippets tagged with the 'verilog' modifier, ensuring they are formatted as proper Verilog code blocks in the generated documentation. Additionally, a utility method for emitting SystemVerilog with specific firtool options (disabling randomization, stripping debug info, and enabling layer specialization) is provided for use within documentation examples.

docs-target · high confidence

The naming module now includes an experimental \HasCustomIdentifier\ trait and \IdentifierProposer\ object, allowing users to provide custom definition identifiers that take precedence over automatically generated ones. This change introduces a new mechanism for identifier proposal where custom definitions are prioritized, followed by plugin-generated identifiers for modules, and finally filtered string proposals for other types, with the \filterProposal\ method ensuring valid character sets by replacing illegal characters with underscores.

core/src/main/scala/chisel3/naming · high confidence

Users can now opt into emitting CIRCT debug intrinsics (circt\_debug\_var, circt\_debug\_subfield, circt\_debug\_enumdef, circt\_debug\_moduleinfo) that carry Chisel type metadata and constructor parameter information, enabling richer debug views in downstream tools. This feature is controlled by the --with-experimental-debug-intrinsics flag or by adding EmitDebugIntrinsicsAnnotation, and includes a SuppressDebugParams marker to prevent duplicate parameter emission for specific data types.

core/src/main/scala/chisel3/debug · high confidence

This change adds a new CIRCT-based compilation backend to Chisel, providing a new \circt.stage.ChiselStage\ as the primary entry point for compiling Chisel designs. Users can now target multiple outputs including CHIRRTL, FIRRTL dialect, HW dialect, and SystemVerilog (with optional splitting into multiple files) via command-line options like \--target\ and \--split-verilog\. The backend supports passing custom options to the \firtool\ binary, configuring the \firtool\ binary path, and preserving aggregate types. It also includes new phases for handling implicit output files, checking configuration consistency, and integrating with the CIRCT compiler infrastructure.

src/main/scala/circt · high confidence

The core/src/main/scala/chisel3/domains location now provides a new ClockDomain abstraction that allows users to define clock domains with explicit relationships. This includes support for synchronous relationships (integer frequency ratios) and rational relationships (non-integer ratios) derived from a common source. The API provides methods to create new domains, derive domains from existing ones, and assert relationships between domains to ensure safe clock domain crossing. A deprecated \derived\ method is included for backward compatibility, recommending the use of \synchronous\ or \rational\ instead.

core/src/main/scala/chisel3/domains · high confidence

A new \DataMirror\ object has been added to \chisel3.reflect\, providing a centralized set of utilities for inspecting Chisel hardware structures. This API allows users to query properties of \Data\ objects, such as determining if they are IO ports, wires, registers, or properties, and checking for probe type modifiers and layer colors. It also includes methods for type equivalence checks (considering alignment, width, and probe info), retrieving module ports by name, and getting early name guesses for hardware nodes.

core/src/main/scala/chisel3/reflect · high confidence

This change introduces the \DataProduct\ typeclass and \DataView\ mapping mechanism within the \chisel3.experimental.dataview\ package, enabling users to create structured views of complex Scala types like \Seq\, \Tuple2\ through \Tuple6\, and \BaseModule\. By providing implicit implementations for these types, the library now supports calling \.viewAs\ on collections and tuples, allowing hardware elements nested within these structures to be mapped to corresponding view fields. This extends the DataView capability beyond simple Bundles, facilitating more flexible hardware abstraction and manipulation for composite data structures.

core/src/main/scala/chisel3/experimental/dataview · high confidence

This change introduces the core Definition and Instance types in the hierarchy package, enabling users to define a module prototype once and instantiate it multiple times. The new API includes the \Definition\ and \Instance\ case classes, a \Hierarchy\ base trait, and a \Lookupable\ typeclass system that allows safe access to internal members (marked with \@public\) from outside the instance context. This replaces the previous do-apply pattern and provides a structured way to handle module cloning, target resolution, and metadata lookup across different instance contexts.

core/src/main/scala/chisel3/experimental/hierarchy/core · high confidence

Chisel now includes a new \chisel3.domain\ package that allows users to define and attach metadata schemas (such as clock, reset, or power domains) to hardware elements. This feature introduces the \Domain\ abstract class for defining schema fields (Boolean, Integer, String) and \Domain.Type\ for representing hardware associated with a specific domain. Users can instantiate domains with specific property values, access subfields via dynamic selection (e.g., \domainPort.field.name\), and use utilities like \domainOf\ to retrieve a wire's domain or \domain.unsafeCast\ to associate data with domains. A basic \domain.Mux\ is also provided for muxing signals while preserving domain associations.

core/src/main/scala/chisel3/domain · high confidence

Added the ModuleChoice API in chisel3.choice, allowing users to define a default hardware module and a set of alternative choices based on specific cases. This feature enables the selection of different hardware implementations at elaboration time, provided all choice modules have type-equivalent I/O bundles, and integrates with the internal InstanceChoiceBinding to generate DefInstanceChoice commands.

src/main/scala/chisel3/choice · high confidence

This change adds a new Scala 3 compiler plugin (located in \plugin/src/main/scala-3\) that implements core Chisel semantics for Scala 3. The plugin introduces \BundlePhase\ to handle Bundle field extraction, cloning, and parent field handling, and \NamingPhase\ to manage automatic naming, including support for tuple unapply patterns and by-name parameters. It also adds \SourceLocatorPhase\ to automatically generate source location information for Module classes. These phases are registered via \ChiselPlugins\ and rely on \PluginHelpers\ for type checking utilities, enabling Chisel to function correctly on the Scala 3 compiler.

plugin/src/main/scala-3 · high confidence

The new \chisel3.util.random\ package provides hardware generators for Linear Feedback Shift Registers (LFSRs), including \FibonacciLFSR\ and \GaloisLFSR\ classes, along with maximal period variants (\MaxPeriodFibonacciLFSR\, \MaxPeriodGaloisLFSR\). These modules support configurable tap points, initial seeds, and reduction operations (XOR or XNOR), and expose a \PRNGIO\ interface for runtime seed loading and conditional incrementing. Companion objects offer convenient \apply\ and \maxPeriod\ methods to generate pseudorandom \UInt\ values directly, with built-in checks to prevent LFSR lockup states.

src/main/scala/chisel3/util/random · high confidence

Chisel now includes a set of default layers that are always emitted in the design output, providing a predictable structure for verification collateral. The new hierarchy places assertions, assumptions, and covers under a root Verification layer, with each sub-layer configured to extract code into specific directories (e.g., verification/assert, verification/assume, verification/cover). Additionally, a Temporal inline layer is introduced as a sub-layer of each verification category, allowing users to guard statements that may not be supported by all simulators or tools, such as certain SystemVerilog assertions.

core/src/main/scala/chisel3/layers · high confidence

This change introduces the \chisel3.properties\ package, providing a new system for handling non-hardware data (Properties) alongside traditional hardware design. Users can now define \Class\ types that act as module-like containers for Property ports, instantiate them via \DynamicObject\ or \StaticObject\, and reference hardware targets using the new \Path\ type. The system supports various Property types including Int, Long, BigInt, Double, String, Boolean, and sequences, enabling the creation of Property graphs and expressions that are distinct from synthesizable hardware.

core/src/main/scala/chisel3/properties · high confidence

Adds svsim, a new low-level library for compiling and controlling SystemVerilog simulations using Verilator and VCS backends. This library provides a backend-independent test harness and simulation controller, allowing higher-level frameworks to build testing capabilities on top of it without being tied to specific technologies like Chisel or ScalaTest. The addition includes the core library code, a Mill build configuration, and documentation explaining the architecture and usage.

svsim, svsim/src · high confidence

The \chisel3.experimental.hierarchy\ package now exposes a new \Definition\ and \Instance\ API, allowing users to create and reuse module definitions via the \Instantiate\ object. This change introduces internal clone classes (\DefinitionClone\, \InstanceClone\, \ModuleClone\) to manage module context and target resolution correctly when instantiating modules from definitions, rather than directly via \Module(...)\. The \Instantiate\ object provides a caching mechanism to ensure that identical module instantiations with the same parameters return the same \Definition\, enabling more predictable and reusable hardware structures.

core/src/main/scala/chisel3/experimental/hierarchy · high confidence

This change introduces a new SerializableModule mechanism in core/src/main/scala-2/chisel3/experimental, allowing Chisel modules with serializable parameters to be generated, cached, and instantiated via Definition and Instance using upickle for serialization. It also adds a private SourceInfoIntf macro interface to handle source location materialization, separating this functionality from coreMacros to prevent accidental invocation in the Chisel frontend.

core/src/main/scala-2/chisel3/experimental · high confidence

Users can now define configuration options using the new \chisel3.choice\ package, which provides \Group\ and \Case\ types for static options and \DynamicGroup\/\DynamicCase\ for runtime-customizable names. These options integrate with the \ModuleChoice\ API, allowing designs to select between different module implementations based on the active option case, facilitating configuration-driven hardware generation.

core/src/main/scala/chisel3/internal · high confidence

The Chisel documentation site has been rebuilt using Docusaurus 3, replacing the previous static site generator. This migration introduces a modern React-based architecture with Algolia-powered search, a new sidebar navigation structure, and a homepage featuring key technology pillars. The site now self-hosts API documentation for both latest stable and snapshot versions, including Scala 3 support, and provides local development workflows via a Makefile that handles dependency installation, build, and serving.

website · high confidence

Added a new BarrelShifter object in the stdlib that provides leftShift, rightShift, leftRotate, and rightRotate operations for Vec types. This utility allows users to perform bitwise shifts and rotations on vectorized data with configurable granularity to trade off between latency and area, offering a more efficient alternative to standard shift operations for certain hardware implementations.

stdlib/src · high confidence

The \chisel3.util.circt\ package now exposes a suite of new intrinsic wrappers that map directly to CIRCT operations, enabling more precise hardware generation and verification. Users can now safely gate clocks with \ClockGate\, invoke SystemVerilog DPI functions via \RawClockedNonVoidFunctionCall\, \RawUnclockedNonVoidFunctionCall\, and \RawClockedVoidFunctionCall\, and construct verification assertions using the new Linear Temporal Logic (LTL) intrinsics (e.g., \LTLAndIntrinsic\, \LTLPastIntrinsic\, \VerifAssertIntrinsic\). Additionally, synthesis-specific utilities like \Mux2Cell\ and \Mux4Cell\ are available to target specific hardware cells, while other intrinsics such as \IsX\, \PlusArgsTest\, \PlusArgsValue\, \SizeOf\, and \MuxCell\ provide direct access to simulator and synthesis features.

src/main/scala/chisel3/util/circt · high confidence

The simulator package introduces a new \SimulatorAPI\ and \EphemeralSimulator\ for running Chisel simulations, replacing the previous \DefaultSimulator\. Users can now explicitly select simulation backends (Verilator or VCS) via the \HasSimulator\ type class, configure randomization of register and memory states, and dynamically enable or disable waveform dumping during simulation using the new \ControlAPI\.

src/main/scala/chisel3/simulator · high confidence

Users can now mix the \ChiselSim\ trait into ScalaTest suites to access simulation APIs (like \simulate\, \peek\, \poke\) and command-line configuration. This integration adds CLI flags for passing options to Chisel elaboration (\-DchiselOpts\) and firtool (\-DfirtoolOpts\), as well as flags to enable waveform dumping at time zero for VCD (\-DemitVcd\), FSDB (\-DemitFsdb\), and VPD (\-DemitVpd\) formats, with backend-specific handling for VCS and Verilator.

src/main/scala/chisel3/simulator/scalatest · high confidence

This change introduces new Scala traits in the \chisel3.testing.scalatest\ package to enhance test infrastructure. The \HasConfigMap\ trait allows tests to access command-line options passed via \-D\ flags through a \configMap\ member. The \TestingDirectory\ trait (exposed via \WithTestingDirectory\) automatically generates structured output directories based on the test suite and test name, implementing the \HasTestingDirectory\ interface. Additionally, a \FileCheck\ trait is provided to combine FileCheck APIs with the new testing directory functionality for easier integration in Scalatest suites.

src/main/scala/chisel3/testing/scalatest · high confidence

A new \SerializableModuleElaborator\ trait has been added to the \chisel3.experimental.util\ package, providing a mixin for generating elaborators for \SerializableModule\ instances. This utility introduces \configImpl\ and \designImpl\ methods that leverage \upickle\ to serialize and deserialize module parameters, allowing users to easily convert parameter configurations into JSON and elaborate designs from those serialized parameters, returning both the FIRRTL circuit and annotations as readable streams.

src/main/scala-2/chisel3/experimental · high confidence

The \chisel3.connectable\ package now provides a new set of connection operators (\:\<=\, \:\>=\, \:\<\>\, and \:\#=\) that allow users to control how hardware components are connected based on field alignment and direction. The \:\<=\ operator connects fields that are aligned (matching direction), \:\>=\ connects flipped fields, \:\<\>\ connects both aligned and flipped fields bidirectionally, and \:\#=\ forces a unidirectional connection from producer to consumer regardless of direction. These operators work with \Data\, \Vec\, \Option\, and \DontCare\, and support customization via \waive\, \squeeze\, and \exclude\ methods to handle missing or mismatched fields without errors.

core/src/main/scala/chisel3/connectable · high confidence

The \chisel3.experimental\ package now includes new capabilities for handling bidirectional analog signals, debugging, and instance naming. Users can define and connect analog ports using the new \Analog\ type and the \attach\ operator, which creates electrical connections between analog components. Debugging is improved with \firrtlComment\, allowing users to insert comments directly into the generated FIRRTL output. Additionally, the \prefix\ and \noPrefix\ objects are now available in this package, enabling users to control naming prefixes for generated hardware instances within specific code scopes.

core/src/main/scala/chisel3/experimental · high confidence

This change introduces several new experimental capabilities in the \chisel3.util.experimental\ package. Users can now control instance optimization during FIRRTL compilation by mixing in \InlineInstance\ or \FlattenInstance\ traits (and their \AllowDedup\ variants) to inline or flatten specific module instances into their parents. Additionally, a new \AutoBlackBox\ class allows users to generate Chisel modules directly from Verilog source strings by parsing them with the Slang tool, automatically inferring the IO bundle and module name. The package also provides \loadMemoryFromFile\ and \loadMemoryFromFileInline\ for initializing memories from external files, and a \getAnnotations\ utility to access the global annotation sequence.

src/main/scala/chisel3/util/experimental · high confidence

Users can now implicitly convert Scala standard library collections and tuples into Chisel hardware types via the new \chisel3.experimental.conversions\ package, which adds implicit conversions for \Seq\ to \Vec\ and tuples of arity 2 through 9 to corresponding \HWTuple\ types using the \DataView\ feature. Additionally, new bitwise utility functions \scanLeftOr\ and \scanRightOr\ have been added to \chisel3.util\, allowing users to compute prefix and suffix logical ORs on \UInt\ values efficiently.

src/main/scala/chisel3/experimental · high confidence

This change introduces several new capabilities in the chisel3 package. It adds FixedIOModule, FixedIORawModule, and FixedIOExtModule, which enforce that a module's IO is determined solely by a provided generator, preventing additional IO creation. It provides SimulationTestHarness, a fixed-IO module with clock/init/done/success signals designed for downstream test drivers like ChiselSim. It introduces a UnitTest trait and a DiscoverUnitTests utility to automatically find and construct test classes from the classpath or runpath. Finally, it adds getVerilogString and emitVerilog objects to generate Verilog output as strings or via command-line arguments using CIRCT.

src/main/scala/chisel3 · high confidence

This change introduces a new simulation framework (ChiselSim) and associated verification APIs. It adds a new \chisel3.simulator\ package containing \Settings\ for controlling simulation parameters (such as layer control, waveforms, and instance choices), \PeekPokeAPI\ for interacting with simulated modules, and \LayerControl\ and \InstanceChoiceControl\ for managing design layers and instance specialization. It also introduces \chisel3.interface\ for defining separable compilation interfaces with \ExtModule\ and \Module\ wrappers, \chisel3.experimental.inlinetest\ for generating inline test harnesses, \chisel3.ltl\ for Linear Temporal Logic assertions, and \chisel3.UnitTestMain\ for discovering and generating unit tests from the classpath.

repository · high confidence

The \chisel3.simulator.stimulus\ package now provides a set of reusable stimulus types to simplify testbench creation. \ResetProcedure\ applies a standardized reset sequence with configurable additional cycles and clock period. \RunUntilFinished\ runs a simulation until a \$finish\ occurs or a timeout is reached. \RunUntilSuccess\ waits for a specific 'success' port to assert within a cycle limit. \SimulationTestStimulus\ runs until a 'done' signal asserts and then checks a 'success' signal, throwing a \TestFailed\ exception if the test does not pass. \InlineTestStimulus\ is deprecated in favor of \SimulationTestStimulus\. These stimuli support both standard Chisel modules and the new \SimulationTestHarnessInterface\.

src/main/scala/chisel3/simulator/stimulus · high confidence

Added the \HasTestingDirectory\ trait and its default implementations to provide a standardized way for tests to manage output directories, including timestamp-based and temporary directory strategies. Introduced the \FileCheck\ trait, which allows tests to run LLVM's FileCheck tool on string inputs to verify generated output, handling file creation, execution, and cleanup automatically.

src/main/scala/chisel3/testing · high confidence

Added Scala 3-specific implementations for the DataView subsystem, including compile-time subtype checking via \ChiselSubtypeOf\ macros and runtime invertibility for total data views through \InvertibleDataView\. The new \ChiselSubtypeOf\ trait enforces that a source type contains all public fields of a target type at compile time, providing clear error messages if structural mismatches occur. The \InvertibleDataView\ extension method allows users to reverse a total \DataView\ mapping, throwing an elaboration-time exception if the view is partial, ensuring safe bidirectional data mapping in Scala 3.

core/src/main/scala-3/chisel3/experimental/dataview · high confidence

This change introduces the Scala 3-specific implementation for the Definition and Instance API within the hierarchy package. It adds macros (InstantiateIntfMacros) to capture module construction arguments at compile time, enabling the creation of Definition and Instance objects. It also implements HierarchyLookupMacro to resolve @public fields on instantiable classes, supporting intersection types and allowing users to access public members of an Instance via dynamic selection (e.g., \inst.field\). The \instantiable\ and \public\ annotations are defined to mark classes and members eligible for this API, and \HierarchyIsA\ provides runtime type checking capabilities for hierarchy instances.

core/src/main/scala-3/chisel3/experimental/hierarchy · high confidence

Added Scala 3-specific implementations of the Select API interface (SelectIntf) in the chisel3.aop package. This enables users to select hardware instances and definitions by type using ClassTag-based reflection on Scala 3, mirroring the existing Scala 2 functionality which relies on TypeTag. The API provides methods to find direct and recursive instances/definitions within a module hierarchy.

src/main/scala-2/chisel3/aop, src/main/scala-3/chisel3/aop · high confidence

Introduces a new structured API in \chisel3.util.experimental.decode\ that allows users to define large decode tables (such as CPU instruction decoders) using \DecodeTable\ and \DecodeBundle\. This API automatically generates the underlying truth table and uses logic minimizers (QMC or Espresso) to produce optimized hardware, replacing manual or less structured decoding approaches.

src/main/scala/chisel3/util/experimental/decode · high confidence

The repository now includes a locally vendored fork of the \com.lihaoyi/unroll\ compiler plugin (version 0.3.0) under \unroll/plugin\. This plugin, built via \unroll/package.mill\, provides compiler phases for both Scala 2 (\UnrollPhaseScala2\) and Scala 3 (\UnrollPhaseScala3\) that generate forwarders for methods with unrolled parameters to ensure binary compatibility. The plugin is registered via \plugin.properties\ and \scalac-plugin.xml\ and depends on the \unroll-annotation\ artifact from Maven.

unroll · high confidence

The core Chisel library files (including Aggregate, Annotation, Bits, BlackBox, BoolFactory, ChiselEnum, Clock, Const, Data, Disable, and ElaboratedCircuit) have been moved from their previous locations into the core/src/main/scala/chisel3 directory. This change restructures the internal organization of the Chisel3 package without altering the public API or behavioral semantics for users.

core/src/main/scala/chisel3 · high confidence

The Chisel 2.x-specific implementations for utility interfaces (BitPat, Bitwise, Cat, Mux, Reg, and Switch) have been moved to the \src/main/scala-2/chisel3/util\ directory and refactored to use private macro interfaces. This change consolidates the Scala 2-specific macro logic for these common hardware components (such as concatenation, multiplexing, and register enabling) into a dedicated location, separating it from the cross-version codebase while maintaining the existing public API for users.

src/main/scala-2/chisel3/util · high confidence

The plugin module now includes a README detailing its core operations: automatically generating \cloneType\ methods for Bundles and rewriting the \elements\ method to avoid reflection (controlled by the \-P:chiselplugin:buildElementAccessor\ flag). The build configuration in \package.mill\ sets up cross-compilation for the plugin, ensuring Java 8 bytecode compatibility via \-release 8\ (with a workaround for early Scala 2.13.x versions) and Scala 3 compatibility (requiring Java 17+ for Scala 3.8+). It also configures separate resource directories for Scala 2 and Scala 3.

plugin · high confidence

The Scala 2 compiler plugin has been restructured into distinct components (BundleComponent, ChiselComponent, IdentifierComponent) to improve code organization and maintainability. Additionally, the plugin now emits a deprecation warning when compiling with Scala versions 2.13.8 or lower, informing users that Chisel 7 will be the final version supporting these older Scala releases.

plugin/src/main/scala-2 · high confidence

The core Chisel interfaces for fundamental types (such as Vec, Bits, Mem, Module, Mux, and VerificationStatement) have been restructured from public veneer classes to private macro traits (e.g., AggregateIntf, BitsIntf, MemIntf). This change moves the implementation of methods like apply, read, write, and arithmetic operations into these private traits, which are mixed into the concrete classes. For users, this is an internal architectural shift that maintains the existing public API surface while enabling better macro expansion and cross-compilation support, without requiring changes to existing hardware generation code.

core/src/main/scala-2/chisel3 · high confidence

The core module's build definition has been migrated to Mill, introducing a new \package.mill\ file that defines the \Core\ module as a \ChiselCrossModule\. This change establishes the build structure for cross-compilation across Scala versions, configures dependencies such as \os-lib\ and \upickle\, and sets up the generation of \BuildInfo.scala\ containing version and toolchain details.

core · high confidence

The internal compiler plugin now marks the \autoNameRecursively\ and \autoNameRecursivelyProduct\ methods as deprecated (since Chisel 7.0.0). These methods now delegate to \chisel3.withName\ and \chisel3.withNames\ respectively. Users should update their code to use the \withName\ API instead of the deprecated recursive naming functions.

core/src/main/scala/chisel3/internal/plugin · high confidence

The annotation system in the firrtl package, including core types like Annotation, Target, and Named, as well as serialization protocols and utility classes, has been marked as deprecated for removal in Chisel 7.0.0. This change signals that these legacy APIs are no longer the primary interface for annotation handling and will be superseded by newer mechanisms in the upcoming major release.

firrtl/src/main/scala/firrtl/annotations · high confidence

The \firrtl.stage.phases\ package, including the \AddDefaults\ and \Checks\ phases, has been deprecated as of Chisel 7.0.0. The \AddDefaults\ phase now handles the injection of default annotations for target directories and info modes, while the \Checks\ phase enforces strict validation of the annotation sequence, ensuring exactly one FIRRTL circuit input, no more than one output file, and exactly one info mode are present. Users relying on these internal stage mechanisms should be aware that these APIs are scheduled for removal.

firrtl/src/main/scala/firrtl/stage/phases · high confidence

The firrtl.memlib package, including MemUtils.scala and ReplaceMemTransform.scala, has been deprecated and will be removed in Chisel 7.0.0. This deprecation affects the --repl-seq-mem command-line option, which previously replaced sequential memories with blackboxes and configuration files. Users relying on this memory replacement pass should prepare for its removal in the next major version.

firrtl/src/main/scala/firrtl/passes/memlib · high confidence

The \firrtl.stage\ package, including \FirrtlOptions\, \FirrtlAnnotations\, and the \FirrtlOptionsView\, is now deprecated as of Chisel 7.0.0. Users relying on these internal stage components for FIRRTL compiler configuration will receive deprecation warnings, signaling that these APIs are scheduled for removal and should be migrated to the supported Chisel interfaces.

firrtl/src/main/scala/firrtl/stage · high confidence

The SourceAnnotation and SinkAnnotation classes in the firrtl.wiring package are now deprecated as of Chisel 7.0.0. Users relying on these annotations for wiring components or modules will receive deprecation warnings, signaling that these APIs are scheduled for removal in future versions.

firrtl/src/main/scala/firrtl/passes/wiring · high confidence

The \firrtl.transforms\ package has been deprecated and is scheduled for removal in Chisel 7.0.0. This change affects users relying on legacy FIRRTL-level annotations for circuit optimization and black-box handling, including \BlackBoxSourceHelper\ (for inline and path-based black boxes), \Dedup\ and \MustDedup\ (for module deduplication groups), \Flatten\ (for module flattening), and \OptimizationAnnotations\ (such as \DontTouchAnnotation\). These APIs are now marked with deprecation warnings to guide migration away from the internal FIRRTL transform system.

firrtl/src/main/scala/firrtl/transforms · high confidence

The \CheckTypes\ pass and \Inline\/\Flatten\ annotations in \firrtl.passes\ are now deprecated as of Chisel 7.0.0. These components, which previously handled type validation and module inlining within the Firrtl compiler pipeline, are marked for removal, signaling that users should migrate to the updated Chisel 5+ compilation flows that no longer rely on these legacy Firrtl-specific mechanisms.

firrtl/src/main/scala/firrtl/passes · high confidence

The legacy \firrtl\ package and its \ir\ subpackage (including \IR.scala\ and \Serializer.scala\) are now deprecated as of Chisel 7.0.0. All classes and traits within these packages, such as \FirrtlNode\, \Info\, \StringLit\, and the \Serializer\, carry a deprecation annotation directing users to migrate to the new serialization and IR APIs. This change signals that the old internal representation structures are no longer the primary interface for Chisel users, who should instead rely on the updated, non-deprecated APIs for IR manipulation and serialization.

firrtl/src/main/scala/firrtl/ir · high confidence

The FIRRTL project has switched its build tool from sbt to Mill, introducing a new \package.mill\ build definition and a \README.md\ that updates installation and usage instructions to reflect this change. This migration includes configuring Scala compiler options (such as \-release:8\ and specific language features) and setting up cross-compilation for multiple Scala versions within the Mill framework.

firrtl · high confidence

The entire \firrtl.options\ package—including the \Stage\, \Shell\, \DependencyManager\, \Phase\, and related annotation and utility classes—has been marked as deprecated and will be removed in Chisel 7.0.0. This change signals that the legacy FIRRTL compiler framework and its associated command-line and annotation-handling infrastructure are no longer the recommended path for new development, urging users to migrate to the newer Chisel APIs.

firrtl/src/main/scala/firrtl/options · high confidence

The \firrtl\ package and its public APIs (including \Compiler\, \Emitter\, \Parser\, \PrimOps\, \RenameMap\, \Utils\, \WIR\, and \AttributeAnnotation\) are now marked as deprecated with a removal target of Chisel 7.0.0. This change signals that these legacy components are no longer the primary interface for users and will be removed in the next major version, encouraging migration to the newer Chisel/FIRRTL abstractions.

firrtl/src/main/scala/firrtl · high confidence

The integration-tests module has been migrated to Mill 1.0.0, replacing the previous build configuration. This change introduces ScalaTest and ScalaCheck as the testing dependencies and enables forked test execution grouped by eight classes to improve performance. The build is configured to run on Scala 2 (via \xsource3 = false\) and includes Scalafmt for code formatting.

integration-tests · high confidence

The internal interface for DynamicObject has been updated to use private macro implementations in Scala 2 and a placeholder trait in Scala 3. This change refactors how Chisel tracks internal state when instantiating DynamicObjects, providing a macro-based apply method for Scala 2 users while maintaining a stub for Scala 3 compatibility.

core/src/main/scala-2/chisel3/properties, core/src/main/scala-3/chisel3/properties · medium confidence

The macros subproject now includes a new scala-2 source directory containing the macro implementations required for Chisel's Scala 2 compilation. This adds the internal machinery for source-info transformation (enabling implicit source location tracking and chained applies), module naming and identifier propagation, runtime deprecation warnings, and the @public/@instantiable annotations for hierarchy support. This change prepares the macros subproject for Scala 3 by isolating Scala 2-specific macro code, ensuring that Scala 2 users retain access to these compile-time transformations while allowing Scala 3 to use alternative mechanisms.

macros/src · high confidence

The LTL public API implementation has been split into separate interface files for Scala 2 and Scala 3 (\LTLIntf.scala\). This change introduces \SequenceIntf\ and \PropertyIntf\ traits that define the available sequence and property operators (such as \delay\, \past\, \repeat\, \implication\, and \always\) for each Scala version, ensuring version-specific syntax compatibility while maintaining a consistent user-facing API for LTL assertions.

src/main/scala-2/chisel3/ltl, src/main/scala-3/chisel3/ltl · high confidence

The macros build module has been updated to conditionally include the scala-reflect dependency only when building for Scala 2. For Scala 3 builds, the dependency is omitted, preventing unnecessary inclusion of Scala 2-specific reflection libraries in Scala 3 artifacts.

macros · high confidence

The lit utility test runner has been migrated from its previous build system to Mill. This change introduces new \package.mill\ files for the \lit\ and \lit/utility\ modules, defining the build structure, cross-compilation for Scala versions, and the execution environment required to run the lit tests (including path configuration for CIRCT binaries).

lit/utility · high confidence

The Chisel documentation website has been migrated to Docusaurus, introducing a new React-based homepage (index.js) that dynamically pulls the site title and tagline from the site configuration, along with a dedicated API documentation page (api.md) that embeds generated ScalaDoc links. The community page (community.md) has also been updated to include new projects such as Tywaves, RISC-V Assembler, and SoC-Now, while maintaining existing community resources and contributor information.

website/src/pages · high confidence

The project has migrated its build infrastructure from SBT to Mill (version 1.0.6, with a wrapper script provided) and switched continuous integration from Travis CI to GitHub Actions. This change introduces a new \build.mill\ configuration, a \flake.nix\ for Nix-based development environments, and automated backporting workflows via Mergify. The build now supports cross-compilation for Scala 2.13 and Scala 3, and the project license has been updated to Apache 2.0.

(repo-wide) · high confidence

The ModuleChoice API has been refactored to use a private macro interface (ModuleChoiceObjIntf) instead of a public veneer. This change introduces a macro-based apply method that delegates to InstChoiceTransform, allowing Chisel to better track internal state during module instantiation based on option choices. Users interacting with ModuleChoice will see no functional change in how they declare options, but the underlying implementation is now more tightly integrated with Chisel's internal macro system.

src/main/scala-2/chisel3/choice · high confidence

The Chisel stage now uses a unified \ChiselOptions\ class to manage configuration, replacing scattered annotation handling with a single source of truth. This change introduces support for several new capabilities: users can now enable legacy width behavior for shift-right operations, remap layer definitions, include utility metadata, use SRAM blackboxes, suppress source info emission, and control the inclusion of inline tests. It also supports treating warnings as errors and configuring specific warning filters, providing finer control over elaboration and error reporting.

src/main/scala/chisel3/stage · high confidence

The internal FIRRTL emission pipeline has been replaced with a new Serializer and Converter architecture that emits FIRRTL version 7.0.0. This change introduces a new internal IR (in \IR.scala\) and a dedicated serialization path (in \Serializer.scala\) that handles modern Chisel features such as Property types, domains, probes, and source locators. The previous Chisel-side FIRRTL emitter has been removed in favor of this new internal implementation, which also includes deprecation shims for legacy \Width\ types in the \package.scala\ stub.

core/src/main/scala/chisel3/internal/firrtl · high confidence

The \firrtl/src/main/scala/logger\ package introduces a new logging infrastructure that allows users to control verbosity via global or per-class log levels, redirect output to a file, and optionally include class names in log entries. This system is configured through command-line options (\--log-level\, \--class-log-level\, \--log-file\, \--log-class-names\) and supports scoped logging via \Logger.makeScope\, ensuring that logging state is isolated during execution. All APIs in this package are deprecated as of Chisel 7.0.0.

firrtl/src/main/scala/logger · high confidence

The annotation handling logic in the FIRRTL options system has been restructured into distinct phase classes (AddDefaults, Checks, GetIncludes, WriteOutputAnnotations) to improve modularity and validation. This change introduces strict validation for target directory and output annotation file specifications, ensures annotation files are recursively included without duplication, and separates the emission of custom file annotations from the main annotation sequence. The WriteOutputAnnotations phase now supports writing circuit-specific annotations via a new WriteableCircuitAnnotation trait, allowing for specialized file emission while maintaining backward compatibility with the standard .anno.json output for non-custom annotations. All APIs in the firrtl.options.phases package are deprecated as of Chisel 7.0.0.

firrtl/src/main/scala/firrtl/options/phases · high confidence

The ModuleChoice API has been updated to support Scala 3 by introducing a new private interface trait (ModuleChoiceObjIntf) and currying the apply method signature to match the Scala 2 form. This change ensures that module instantiation based on option choices remains compatible with Scala 3's macro system while preserving the existing user-facing behavior for selecting alternative module implementations.

src/main/scala-3/chisel3/choice · high confidence

The \Instantiate\ API in the hierarchy package has been switched from a veneer implementation to a private macro interface. This change introduces new Scala 2-specific files (\InstantiateIntf.scala\, \HierarchyPackage.scala\, \IsA.scala\) that define the \instantiable\ and \public\ annotations and implement the macro logic for \Instantiate.apply\ and \Instantiate.definition\. For users, this represents an internal restructuring of how module instances and definitions are created, likely to support better Scala 3 cross-compilation and stricter type safety, while maintaining the same public API surface for creating \Instance\ and \Definition\ objects.

core/src/main/scala-2/chisel3/experimental/hierarchy · high confidence

The stdlib build definition has been restructured to use a new \package.mill\ file that defines a \Stdlib\ module extending \HasScalaPlugin\, \HasCommonOptions\, and \ScalafmtModule\. This change introduces a cross-build mechanism via a \Cross\[Stdlib\]\ object, allowing the stdlib to be built against multiple Scala versions as defined by \scalaCrossVersions\. The module explicitly depends on the \chiselModule\ and adjusts its directory context relative to the parent module.

stdlib · high confidence

The probe package internals have been restructured to use new private base traits (ProbeBase, ProbeValueBase) for creating and handling probe types, moving away from previous implementation patterns. This change also modifies the probe force and release APIs by removing the explicit clock and condition parameters, which are now automatically derived from the builder context (forced clock and disable option), simplifying the user-facing API for forcing and releasing writable probes.

core/src/main/scala/chisel3/probe · high confidence

The Chisel compilation pipeline has been refactored from a monolithic structure into a series of distinct, composable phases (Elaborate, Checks, Convert, Emitter, etc.) that manage the lifecycle of circuit annotations. This change introduces explicit handling for output file generation (AddImplicitOutputFile), annotation file writing (AddImplicitOutputAnnotationFile), and circuit serialization (AddSerializationAnnotations), while deprecating the legacy Convert phase in favor of direct ElaboratedCircuit usage. It also adds new capabilities for debug instrumentation (AddDebugIntrinsics) and automatic deduplication grouping (AddDedupGroupAnnotations), providing users with a more transparent and extensible stage mechanism for controlling elaboration and emission behavior.

src/main/scala/chisel3/stage/phases · high confidence

The \ChiselSubtypeOf\ trait and \InvertibleDataView\ functionality have been moved to the Scala 2 source directory to support cross-compilation. This change ensures that structural subtype checks for Chisel Bundles and the inversion of total DataViews function correctly on Scala 2, while providing an empty macro implementation for Scala 3 compatibility.

core/src/main/scala-2/chisel3/experimental/dataview · high confidence

The Scala 2-specific probe interface in \core/src/main/scala-2/chisel3/probe\ has been restructured into dedicated veneer files (\PackageIntf.scala\, \Probe.scala\, \ProbeValue.scala\) that delegate to macro implementations. This change introduces the ability to create RWProbes with layer colors (via \RWProbe.apply(source, color)\) and provides corresponding read/write probe value objects (\RWProbeValue\), enabling users to annotate probes with layer information directly in Scala 2 builds.

core/src/main/scala-2/chisel3/probe · high confidence

A new Scala 2-specific macro implementation for SourceInfoMacro has been added to the core library. This file provides the macro logic required to capture source location information (file path, line, and column) at the point of invocation, ensuring that Chisel designs generate accurate source line metadata when compiled with Scala 2. This change supports the broader effort to maintain Scala 2 compatibility alongside the new Scala 3 implementation.

core/src/main/scala-2/chisel3/internal · high confidence

The Scala 3-specific SourceInfo mechanism has been updated to use a private macro interface (SourceInfoIntf) that delegates to SourceInfoMacro.generate\_source\_info. This ensures source locators are generated only at the point of invocation in the Chisel frontend, preventing accidental generation of locators within the Chisel core itself.

core/src/main/scala-3/chisel3/experimental · high confidence

The Scala 3 core module now provides a complete interface layer that replaces the previous veneer pattern with private macro interfaces for core types including Bits, Vec, Bundle, Mem, Module, Mux, and verification statements. This change introduces Scala 3-specific features such as the ChiselEnum macro for compile-time enum value generation, a BundleSelect extension for accessing anonymous Bundle fields, and a FormalContract macro for type-safe formal verification contracts. Users benefit from improved type safety, better source location tracking via SourceInfoMacro, and native support for Scala 3's macro system while maintaining API compatibility with existing Chisel designs.

core/src/main/scala-3/chisel3 · high confidence

The Scala 3 probe package has been restructured to use private macro interfaces, introducing new objects for creating probes. Users can now create layer-colored read-write probes using \RWProbe\ and \RWProbeValue\, which accept an optional \layer.Layer\ color argument, alongside standard \Probe\ and \ProbeValue\ for read-only access. A \read\ function is also provided to access the value of a probe, ensuring parity with the Scala 2 API while supporting the new layer coloring feature.

core/src/main/scala-3/chisel3/probe · high confidence

The Scala 3 \chisel3.util\ package now provides its own interface definitions and macro-based implementations for core hardware utilities. New interface files (\BitPatIntf\, \BitwiseIntf\, \CatIntf\, \MuxIntf\, \RegIntf\) expose methods for \BitPat\, bitwise operations (\Fill\, \PopCount\, \Reverse\), concatenation (\Cat\), multiplexing (\Mux\, \PriorityMux\, \MuxLookup\), and registers (\RegEnable\, \ShiftRegister\). Additionally, a new \Switch.scala\ file introduces a compile-time macro for \switch\/\is\ blocks, enabling multi-argument \is()\ cases and improved type safety compared to the previous veneer approach. A \util.scala\ package object also re-exports \ValidIO\ for compatibility.

src/main/scala-3/chisel3/util · high confidence

A new plugin.properties file has been added for Scala 3, explicitly registering chisel3.internal.plugin.ChiselPlugins as the plugin class. This change supports the split of plugin resource files based on Scala major version, ensuring the correct plugin implementation is loaded for Scala 3 projects.

plugin/src/main/resources-3 · high confidence

The Chisel3 simulation template (top.cpp) has been updated to prevent toggling the clock and reset signals on the same cycle. Reset is now deasserted at simulation time 10, while the clock toggles begin at time 11. This staggered approach ensures consistent simulation behavior regardless of whether the generated Verilog places synchronous reset logic inside or outside its associated always block.

src/main/resources · high confidence

The website's static directory has been updated to support the migration to Docusaurus. This includes adding a CNAME file for the www.chisel-lang.org domain, a .nojekyll file to prevent GitHub Pages from processing the site with Jekyll, and a robots.txt file that allows crawling of the main site while disallowing the /api/snapshot/ path. Additionally, several new SVG images have been added to the static/img folder, including logos for Chips Alliance, Chisel Tool, Firrtl Tech, Firrtl, and Scala.

website/static · high confidence

The website's visual presentation has been updated with new branding colors (Chisel logo blue \#212560 for light mode, Cal gold \#FDB515 for dark mode) and a new ChipsAlliance logo in the header. Link colors are now more distinct for better readability, especially in dark mode, and the Table of Contents styling has been adjusted to resemble standard Markdown lists.

website/src/css · high confidence

Add FirrtlSpec test utilities; Add cookbook tests for data type conversions and FSMs; Added Lit test infrastructure and initial test cases; Added TestUtils helper for emitting warnings in tests; Added Verilog test resources for Chisel3 black box and FSM testing; Added comprehensive test coverage for the new Chisel simulator infrastructure; Added comprehensive test suite for Chisel hardware constructs; Added integration tests for the CIRCT converter; Added test coverage for CIRCT stage entry points; Added test coverage for FIRRTL options infrastructure; Added test resources for ChiselSim library linking; Added test resources for error caret testing; Added test suite for the experimental Hierarchy API; Added tests for AddImplicitOutputFile phase; Added tests for BitPat, GrayCode, and TruthTable utilities; Added tests for CIRCT intrinsic utilities; Added tests for Chisel interface conformance and parametric interfaces; Added tests for Chisel naming and prefixing mechanisms; Added tests for Chisel stage annotations and warning configuration; Added tests for Chisel utility functions; Added tests for ChiselOptionsView; Added tests for ChiselSim simulation behavior and CLI options; Added tests for ChiselTest example modules; Added tests for DataMirror reflection capabilities; Added tests for DataView reification and identity view distinction; Added tests for FIRRTL 7.0.0 ExtModule serialization and Serializer behavior; Added tests for FirrtlOptionsView behavior; Added tests for IO direction handling and Bundle cloning; Added tests for OpaqueType, SerializableModuleGenerator, and SerializableModuleElaborator; Added tests for PLA generation and BoringUtils tapAndRead; Added tests for PRNG step sizes and seed updates; Added tests for Placeholder API, Select API, and Type Equivalence checks; Added tests for Property and DynamicObject features; Added tests for Property type validation and support; Added tests for SparseVec behavior and equivalence; Added tests for annotation serialization overrides and type hints; Added tests for debug intrinsic emission and constructor parameter reflection; Added tests for experimental Chisel APIs; Added tests for internal Chisel utilities; Added tests for module identifier naming and custom identifier proposals; Added tests for module port conventions and output directory annotations; Added tests for testing utilities and directory management; Added tests for the Property API and Class/Object support; Added tests for the aop.Select API; Added tests for the structured decoder DecodeTable utility; Added unit tests for Chisel stage phases; Added unit tests for DiGraph graph operations; Added unit tests for FIRRTL annotation serialization and target handling; Added unit tests for FIRRTL options phases; Added unit tests for FIRRTL stage phase defaults and checks; Added vending machine cookbook examples; Migrate integration tests to ChiselSim.

The website's dependency manifest has been updated to use Docusaurus 3.10.2 (up from 3.1.1) and React 19.2.0. The package configuration also includes overrides for qs, serialize-javascript, and uuid to address security vulnerabilities, alongside a requirement for Node.js version 18.0 or higher.

(dependencies) · high confidence

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

• CAI 45 → 67 (+21.4)
• Rubric changed (rubric-2026.08.15 → rubric-2026.09.15) — scores are not directly comparable.

• Code Health 99 → 85 (-13.6)
• Architecture 69 → 97 (+28.2)
• Maturity 61 → 76 (+15.0)
• Readiness 26 → 58 (+32.5)
• Security 56 → 63 (+7.2)
• Domain Modelling 100 (new)

• Coverage not measured — test suite did not build
• Dimension evaluation failed
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• High: security finding (details withheld)
• …and 21 more

• Backend.generateParameters (cyclomatic 20) (svsim/src/main/scala/verilator/Backend.scala)
• Backend.generateParameters (cyclomatic 21) (svsim/src/main/scala/vcs/Backend.scala)
• BiConnect.connect (cognitive 59) (core/src/main/scala/chisel3/internal/BiConnect.scala)
• BiConnect.connect (cyclomatic 36) (core/src/main/scala/chisel3/internal/BiConnect.scala)
• BiConnect.elemConnect (cognitive 17) (core/src/main/scala/chisel3/internal/BiConnect.scala)
• BiConnect.elemConnect (cyclomatic 38) (core/src/main/scala/chisel3/internal/BiConnect.scala)
• BoringUtils.boreOrTap (cognitive 44) (src/main/scala/chisel3/util/experimental/BoringUtils.scala)
• BoringUtils.boreOrTap (cyclomatic 33) (src/main/scala/chisel3/util/experimental/BoringUtils.scala)
• CIRCT.transform (cognitive 27) (src/main/scala/circt/stage/phases/CIRCT.scala)
• CIRCT.transform (cyclomatic 42) (src/main/scala/circt/stage/phases/CIRCT.scala)
• Change coupling: Converter.scala ↔ Serializer.scala (core/src/main/scala/chisel3/internal/firrtl/Converter.scala)
• Change coupling: Converter.scala ↔ Serializer.scala (core/src/main/scala/chisel3/internal/firrtl/Converter.scala)
• ChiselNamingPhase.collectUnapplyNames (cognitive 22) (plugin/src/main/scala-3/chisel3/internal/plugin/NamingPhase.scala)
• ChiselNamingPhase.transformValDef (cognitive 39) (plugin/src/main/scala-3/chisel3/internal/plugin/NamingPhase.scala)
• ChiselNamingPhase.transformValDef (cyclomatic 24) (plugin/src/main/scala-3/chisel3/internal/plugin/NamingPhase.scala)
• ChiselSubtypeOf.genChiselImpl (cognitive 16) (core/src/main/scala-3/chisel3/experimental/dataview/ChiselSubtypeOf.scala)
• Connection.doConnection (cognitive 22) (core/src/main/scala/chisel3/connectable/Connection.scala)
• Connection.doConnection (cyclomatic 29) (core/src/main/scala/chisel3/connectable/Connection.scala)
• Converter.convert (cyclomatic 24) (core/src/main/scala/chisel3/internal/firrtl/Converter.scala)
• Converter.extractType (cyclomatic 24) (core/src/main/scala/chisel3/internal/firrtl/Converter.scala)
• …and 369 more

• 28 commits — 26 feature/other, 2 fixes

• website/package-lock.json — 5 commits
• core/src — 4 commits
• etc/circt.json — 4 commits
• (root) — 2 commits
• .github/workflows — 2 commits
• docs/src — 2 commits
• etc/previous-versions.txt — 2 commits
• src/main — 2 commits
• src/test — 2 commits
• docs/README.md — 1 commit
• lit/tests — 1 commit
• macros/src — 1 commit

• fix: Fix @public constructor vals in Scala 2 (#5485)
• fix: [scala3] Fix return type of .pad (#5486)
• change: Always print stderr from firtool in CIRCT phase (#5464)
• change: Bump Docusaurus to 3.10.2 (#5488)
• change: Bump browserslist from 4.28.1 to 4.28.8 in /website (#5480)
• change: Bump fast-uri from 3.1.5 to 3.1.7 in /website (#5479)
• change: Bump js-yaml from 3.14.2 to 3.15.1 in /website (#5461)
• change: Bump postcss-selector-parser in /website (#5477)
• change: Enable MiMa for v7.14.0 (#5466)
• change: Enable MiMa for v7.15.0 (#5478)
• change: Make FileCheck directory clearing more robust (#5474)
• change: Preserve literals in Cat (#5492)
• change: Update Github Actions (#5468)
• change: Update docs/README.md (#5441)
• change: [Data] Distinguish LHS/RHS in connect/bulkConnect hardware error (#5491)
• change: [build] Ignore generated website API docs (#5467)
• change: [cd] Bump CIRCT from firtool-1.154.0 to firtool-1.155.0 (#5460)
• change: [cd] Bump CIRCT from firtool-1.155.0 to firtool-1.156.0 (#5470)
• change: [cd] Bump CIRCT from firtool-1.156.0 to firtool-1.157.0 (#5472)
• change: [cd] Bump CIRCT from firtool-1.157.0 to firtool-1.158.0 (#5476)
• …and 8 more

• Containers 0 added · 0 removed · contexts 5 added · 0 removed · edges 14 added · 0 removed

• core
• firrtl
• plugin
• repository
• svsim

• core → firrtl (coupling)
• core → repository (coupling)
• core → svsim
• firrtl → core (coupling)
• firrtl → repository (coupling)
• firrtl → svsim
• plugin → core
• plugin → firrtl
• plugin → svsim
• repository → core (coupling)
• repository → firrtl (coupling)
• repository → svsim (coupling)
• svsim → core (coupling)
• svsim → repository (coupling)

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

chipsalliance/chisel was measured the same way every project in this corpus was: the same rubric, at a pinned commit, with the result published in full. Point a surveyor at a repository you know and see whether you agree with it.