chipsalliance/t1

This system is a comprehensive RISC-V hardware and software development environment centered on the T1 vector processor and the Pokedex reference model. It provides a full-stack toolchain for generating, simulating, and verifying RISC-V designs, featuring extensive support for the Vector ISA, floating-point arithmetic, and cryptographic primitives. The infrastructure integrates Chisel-based hardware generation, MLIR-based compilation flows, and Rust/C++ co-simulation tools to enable rigorous diff-testing against the Spike emulator.

46 changes.

The project migrated its build infrastructure from Mill to Nix Flakes, establishing reproducible environments for the T1 vector processor, emulator, and test suites. This period focused on rewriting core components in Rust, expanding RISC-V Vector ISA compliance through extensive MLIR and assembly test coverage, and integrating PyTorch end-to-end validation.

35 changes.

This period focused on the initial release and expansion of the Pokedex RISC-V model, implementing core architectural states, instruction sets (RVV, RV-A, Compressed, F-extension), and CSR handling. Concurrently, the project established a robust Nix-based build system for Pokedex and other components, integrated the Berkeley HardFloat library, and introduced offline simulation verification tools like t1-sim-checker.

5 changes.

This period focused on expanding the hardware library with new arithmetic, cryptographic, and vector processing modules, including adders, dividers, and VRF dependency checking. Concurrently, the project established a robust Nix-based build and dependency management system for these new components. Comprehensive formal and simulation test suites were also added to verify the correctness of the newly implemented hardware designs.

The pokedex CSR model now includes implementations for key Machine Mode registers (mvendorid, marchid, mimpid, mhartid, mconfigptr, mstatus, misa, mie, mtvec, mstatush, mscratch, mepc, mcause, mip) alongside Vector extension registers (vl, vtype, vlenb, vstart, vxsat, vxrm, vcsr) and Floating-Point registers (fflags, frm, fcsr). These additions enable the simulator to handle privilege-level checks, trap handling, interrupt management, and vector/floating-point state tracking as defined by the RISC-V specification.

pokedex/model/csr · high confidence

The RV Zicsr extension model now includes implementations for the CSR read-modify-write instructions: CSRRW, CSRRWI, CSRRS, CSRRSI, CSRRC, and CSRRCI. These new files define the execution logic for reading the current CSR value, performing bitwise OR or AND-NOT operations with a source register or immediate, writing the result back to the CSR, and updating the destination register, thereby completing the support for this subset of the Zicsr standard extension.

_pokedex/model/extensions/rv\zicsr · high confidence

Added a set of Scala elaborators in the \elaborator/src/rocketv\ directory to generate configuration and design files for RocketV components, including the ALU, AMOALU, BTB, BreakpointUnit, CSR, DCache, Decoder, FPU, Frontend, ICache, MulDiv, PMAChecker, PTW, and Rocket core.

repository · high confidence

The t1-sim-checker now includes a new offline verification module for the T1 Rocket emulator. This addition introduces a SpikeRunner-based engine that reads RTL event logs (JSON) and replays them to validate register writes (integer and floating-point), vector register file (VRF) updates, memory operations, and instruction scheduling against the expected hardware behavior.

difftest/t1-sim-checker/src/t1rocketemu · high confidence

This change introduces new hardware modules for the t1zaozi RTL: VRF (Vector Register File) dependency checking logic in ChainingCheck and WriteCheck to handle read-after-write and write-after-read hazards, a ZVMAProcessingElement for vector matrix multiply-accumulate operations with pipelined execution and internal state RAM, and a set of utility functions in Utils.scala for bit manipulation. It also adds Verilog SRAM models (SRAM1R1W, SRAM1RW, SRAM2RW) to support these components, with SRAM1RW specifically included as a temporary workaround for the zaozi VerilogWrapper.

t1zaozi · high confidence

The berkeley-hardfloat dependency is now included as a Git submodule, bringing in its Chisel-based hardware floating-point units. A Mill build definition (build.mill) is provided to compile the library against Chisel versions 3.5.6, 3.6.0, and 5.0.0 using Scala 2.13.18, and a GitHub Actions workflow is added to run automated testing via both Mill and SBT across multiple Java versions (8, 11, 17).

dependencies/berkeley-hardfloat · high confidence

The project now includes the Berkeley HardFloat IEEE floating-point arithmetic package as a submodule under \dependencies/berkeley-hardfloat/hardfloat\, integrated with Mill 0.12. This adds a suite of Chisel-based hardware modules for standard floating-point operations, including addition, multiplication, fused multiply-add, division, square root, comparison, and integer-to-float conversion. These components provide configurable exponent and significand widths and support various rounding modes and exception flag reporting, enabling precise hardware-level floating-point arithmetic in designs that depend on this library.

dependencies/berkeley-hardfloat/hardfloat · high confidence

A new Scala entry point (LaneShifter) has been added to the elaborator module, enabling users to generate the LaneShifter hardware design via command-line arguments for datapath width and latency, or by loading parameters from a JSON file to produce FIRRTL and annotation outputs.

elaborator · high confidence

The \V.scala\ file in the CSR module now defines the \V\ class, which manages the state registers for the RISC-V Vector extension. This includes standard vector context registers such as \vl\, \vtype\ (via \vsew\, \vlmul\, \vta\, \vma\, \vill\), \vstart\, \vxrm\, and \vxsat\, along with hypervisor support via \vsstatus\. Additionally, when the \xsfmm\ configuration is enabled, the implementation includes support for the ZVMA extension registers (\tm\, \tk\, \vtwiden\, \altfmt\).

rocketv/src/csr · high confidence

The custom-instructions directory now includes the \rv\_xsfmm\ file, which defines the opcode encodings for the ZVMA vector matrix multiply-accumulate extension. This addition enables support for specific vector operations including element-wise comparisons (vlte), storage (vste), matrix multiply (mm), and vector transpose/move (vtmv, vtzero, vtdiscard) instructions required for the ZVMA feature.

custom-instructions · high confidence

A new \HasExtModuleDefine\ trait has been added to the \chisel3.probe\ package, providing \define\ and \defineVec\ methods that allow users to create probe signals for BlackBoxes. This enables external modules to expose internal signal paths as probes, facilitating better visibility and debugging of internal states within hardware designs.

emuhelper · high confidence

The Pokedex model now includes execution logic for a comprehensive set of RISC-V Compressed (C) instructions, covering arithmetic (add, addi, addi16sp, addi4spn, li, lui, slli, sub, xor, or, and, mv), logical (andi), control flow (j, jal, jalr, jr, beqz, bnez), and memory operations (lw, lwsp, sw, swsp). It also adds support for the Compressed Floating-Point (CF) extension with flw, flwsp, fsw, and fswsp, including proper handling of the FS status enable check and dirty bit management. These changes allow the simulator to correctly execute code utilizing these compact instruction formats.

_pokedex/model/extensions/rv\c · high confidence

The Pokedex model now includes explicit ASL (Abstract State Language) implementations for a broader set of RISC-V instructions, covering arithmetic (ADD, SUB, MUL, DIV, etc.), logical (AND, OR, XOR), immediate variants (ADDI, ANDI, etc.), load/store (LB, LH, LW, SB, SH, SW), branch (BEQ, BNE, BLT, etc.), and jump (JAL, JALR) operations. It also adds support for privileged instructions (MRET, WFI) and system calls (ECALL, EBREAK). This change provides a more complete functional model for the emulator, allowing it to execute a wider range of standard RISC-V code.

_pokedex/model/extensions/rv\_im\zifencei · high confidence

The pokedex model now includes explicit execution logic for the RISC-V Atomic (RV-A) extension, specifically for 32-bit operations. This adds support for atomic memory operations (AMOSWAP, AMOAND, AMOOR, AMOXOR, AMOADD, AMOMAX, AMOMAXU, AMOMIN, AMOMINU) via the new \amoadd\_w.asl.j2\ template, as well as Load-Reserved (\lr\_w.asl\) and Store-Conditional (\sc\_w.asl\) instructions. These implementations handle address alignment checks and interact with the foreign function interface (FFI) to simulate atomic behavior, raising access fault exceptions for misaligned addresses.

_pokedex/model/extensions/rv\a · high confidence

The RVV memory model extension now supports indexed load (VLOXEI) and store (VSOXEI) instructions, which use offsets from a vector register to calculate memory addresses, as well as strided load (VLSE) and store (VSSE) instructions, which use a stride value from a general-purpose register. These additions complement the existing contiguous and segment-based memory operations, enabling more flexible data access patterns for vectorized code.

_pokedex/model/extensions/rv\vmem · high confidence

This change introduces the Pokedex project, providing a configurable RISC-V model, a simulator, and associated documentation. The Nix build system is set up to generate documentation via the command \nix build '.\#pokedex.\<config\>.docs.guidance'\, with build artifacts and generated files (such as JSONL and PDFs) excluded from version control.

pokedex · high confidence

This change adds the Nix build system files for the T1 project, establishing a reproducible environment for compiling Mill modules (elaborator, omreader, t1zaozi) and generating hardware artifacts. It introduces a scope that exposes configuration parsing, conversion utilities (Chisel-to-MLIRBC, Zaozi-to-MLIRBC, FIRRTL linking, MLIRBC-to-SystemVerilog), and emulator builders (Verilator and VCS). The infrastructure supports generating RTL, metadata, and test cases for various T1 configurations, including specific ZVMA and lane modules, while integrating with existing dependency locks and toolchains like CIRCT and MLIR.

nix/t1 · high confidence

The repository now provides a Nix overlay (nix/overlay.nix) that exposes a comprehensive set of build artifacts and tools as Nix packages. This includes the core build environment (rv32-stdenv), cross-compilation toolchains (riscv32-embedded), and specific libraries such as LLVM compiler-rt, newlib, and emurt. The overlay also integrates external dependencies and internal tools, including Buddy-MLIR, IREE (runtime, Python bindings, and Turbine), DRAMSim3, RISC-V vector tests, and the ASL interpreter. This change centralizes dependency management and ensures reproducible builds for the emulator and test infrastructure.

nix · high confidence

Added a new \pokedex/model/scripts\ package containing \buildgen.py\, \datagen.py\, \doccomment.py\, and supporting utilities (\ninja\_syntax.py\, \riscv\_opcodes.py\, \riscv\_opcodes\_util.py\). These scripts enable config-driven generation of Ninja build files, parsing of RISC-V instruction encodings from external sources, and extraction of documentation comments into YAML metadata, replacing previous ad-hoc or manual processes with a structured, automated pipeline.

pokedex/model/scripts · high confidence

The difftest component now includes a new Rust crate (spike\_rs) that provides a native Rust interface to the Spike RISC-V simulator. This change replaces the previous C++/DPI-based trampoline with a direct FFI binding, allowing the diftest runner to load ELF binaries, execute instructions, and capture architectural events (such as register writes, memory accesses, and vector state) directly within the Rust test harness. The implementation handles memory mapping, instruction stepping, and event logging for both scalar and vector instructions, enabling more robust and maintainable hardware-software co-verification.

_difftest/spike\rs · high confidence

A new TestBench module has been added to the emulator to drive the T1 core via external Verilog functions (issue\_vector\_instruction, retire\_vector\_instruction, retire\_vector\_mem) and AXI4 slave agents for memory access. The testbench now passes configuration parameters such as vLen, dLen, lane width, and the Spike ISA string (with xsfmm filtered out) to the Verilog module, and logs VRF write events to a JSONL file for difftest and performance modeling.

t1emu/src · high confidence

The T1 Rocket Emulator DPI now supports an asynchronous AXI memory interface, allowing memory requests (AW, W, AR channels) to be pushed and responses (B channel) to be popped independently rather than blocking on a single tick. This change introduces new DPI functions (\axi\_push\_AW\, \axi\_push\_W\, \axi\_push\_AR\, \axi\_pop\_B\) and internal structures (\IncompleteRead\, \IncompleteWrite\) to manage out-of-order and pipelined memory transactions, improving simulation throughput and fidelity for complex memory systems.

_difftest/dpi\t1rocketemu/src · high confidence

A new Rust crate, \dpi\_common\, has been added to provide shared utilities for the DPI-based simulation environment. It includes a \DpiTarget\ generic wrapper for safely managing initialized simulation targets, a \PlusArgMatcher\ for parsing Verilog-style command-line arguments, and a \MetaConfig\ struct to hold CPU configuration details. Additionally, it provides a \write\_perf\_json\ function that outputs simulation results (including cycle counts, success status, and memory model settings) to \sim\_result.json\, and a logger setup function using \tracing\.

_difftest/dpi\common · high confidence

A new offline verification tool, t1-sim-checker, has been added to the difftest suite. This utility reads a simulation result JSON file and an RTL event log to perform offline diff checks against Spike. It supports multiple simulation flavors (t1emu, t1rocketemu) and allows users to override key configuration parameters such as VLEN, DLEN, lane width, and ISA via command-line arguments, providing a flexible way to validate RTL behavior against reference models without requiring an online run.

difftest/t1-sim-checker/src · high confidence

A new Main.scala entry point has been added to the script/emu module, providing a structured command-line interface for managing emulator workflows. This script introduces capabilities for resolving test artifacts (ELFs, coverage data, and benchmarks) via Nix attributes, managing output directories with timestamped results and symlinks, and handling file operations such as copying directories with specific permission and link-following behaviors. It also implements a basic logging system with configurable levels and a simple JSON-based caching mechanism for helper data, effectively centralizing the orchestration logic previously handled by disparate shell scripts.

script/emu · high confidence

A new C++ library (spike\_interfaces) is introduced to provide a stable C-compatible interface for interacting with the Spike RISC-V simulator in difftest workflows. This library exposes functions to instantiate the simulator with configurable vector lane widths and counts, retrieve processor state (PC, registers, vector registers), execute instructions, and manage simulation state, enabling the difftest harness to bridge between the test environment and the Spike backend.

_difftest/spike\interfaces · high confidence

This change introduces a new Rust-based DPI (Direct Programming Interface) driver for the t1emu simulation environment. The driver implements AXI memory access handlers (high-bandwidth and indexed access ports) to bridge the Verilog testbench with a Spike RISC-V emulator. It manages a shadow memory model, handles AXI strobe/data payload parsing, and configures the emulator with specific ISA, vector length (vlen), and data length (dlen) parameters passed from the simulation. This allows the t1emu component to execute instructions and handle memory transactions via the Spike backend during co-simulation.

_difftest/dpi\t1emu · high confidence

The release process now generates a Docker image and a manual for the T1 emulator environment. The Nix expression \docker-image.nix\ defines the image contents, including a \t1-cc\ compiler wrapper, example test cases, and the \cmake\ build tool. A new \doc.nix\ derivation uses Typst and Pandoc to build a PDF and Markdown manual (\doc.typ\) that explains how to compile and run examples, configure memory regions, and use the provided simulator variants within the container.

nix/t1/release · high confidence

The emulator now includes dedicated MMIO devices for handling display output and simulation lifecycle. A new FrameBuffer device maps VRAM to a 960x720 RGB24 buffer and exposes control registers that allow flushing the current frame as a PNG image to disk (configurable via DISP\_OUT\_DIR). Additionally, a SimCtrl device manages simulation termination via a specific exit code (0xdead\_beef) and records UART and profile write events to an mmio-event.jsonl file for external analysis.

_difftest/dpi\t1rocketemu/src/interconnect · high confidence

This change introduces a new set of Nix build modules in the \nix/t1/conversion\ directory to automate the T1 hardware design flow. The new infrastructure provides builders for converting Chisel and Zaozi designs into MLIR bytecode (\chisel-to-mlirbc.nix\, \zaozi-to-mlirbc.nix\), finalizing MLIR bytecode (\finalize-mlirbc.nix\), and linking circuits (\firld-link.nix\). It also includes conversion steps from MLIR bytecode to SystemVerilog (\mlirbc-to-sv.nix\) and dedicated builders for generating VCS simulators (\sv-to-vcs-simulator.nix\) and Verilator emulators (\sv-to-verilator-emulator.nix\). These modules standardize the build process, supporting features like coverage, tracing, and DPI library linking within the Nix environment.

nix/t1/conversion · high confidence

A new Scala application (script/ci/src/Main.scala) has been introduced to manage CI workflows. It replaces previous shell-based logic by reading test definitions from JSON files, scheduling them into balanced buckets for parallel execution via GitHub Actions matrices, and running the simulations. The script supports both Verilator and VCS emulators, handles test result reporting (including failure logs and cycle update reports), and allows configuration of runner counts and test directories.

script/ci · high confidence

A new \TestBench.scala\ file introduces the testbench infrastructure for the T1Rocket emulator. This component instantiates the \T1RocketTile\ and connects it to AXI4 slave agents for high-bandwidth, high-outstanding, instruction fetch, and load-store channels, configuring specific payload sizes for each. It also integrates a \VerbatimModule\ (previously \ClockGen\) for clock/reset handling, exposes probe data for registers and LSU units, and logs simulation events such as register writes to a JSONL file.

t1rocketemu/src · high confidence

A new VerbatimModule has been added to handle simulation infrastructure that cannot be expressed in Chisel, including clock generation, plusarg parsing, and simulation control. This module introduces a new logging package (\_\_circt\_lib\_logging) that manages RTL event recording via file descriptors, supporting configuration through plusargs like +t1\_dev\_rtl\_event\_off and +t1\_dev\_rtl\_event\_path. It also handles the initialization of the cosimulation interface (t1\_cosim\_init) with parameters for data length, lane width, vector length, and ISA, while managing watchdog timeouts and debug wave dumping capabilities.

t1rocketemu/vsrc · high confidence

The \dependencies/arithmetic\ library now includes a comprehensive set of new Chisel3 hardware modules for arithmetic and cryptography. This adds support for various addition algorithms, including Ripple Carry, Kogge Stone, and Brent Kung prefix adders, as well as Carry Save Adders (CSA) with compressors. It also introduces SRT division units (radix 4, 8, and 16) with their associated tables and I/O definitions. On the cryptography side, the library now provides a ChaCha stream cipher implementation and modular multiplication units using Barrett and Montgomery reduction methods.

(repo-wide) · high confidence

A new Rust-based profiler has been added to the project, allowing users to analyze VCD (Value Change Dump) simulation traces. The tool reads VCD input files and outputs various analysis results to a specified directory. It includes support for instruction disassembly via the \spike-dasm\ utility (configured via the \SPIKE\_DASM\ environment variable), which integrates with the profiling data to provide instruction-level insights.

profiler · high confidence

The pokedex model now includes a comprehensive set of handwritten ASL files that define the core architectural state and execution logic. This includes explicit definitions for architectural states such as the Program Counter, General Purpose Registers (GPR), Floating-Point Registers (FPR), and Vector Registers (VRF), along with their associated control registers (CSR) like MSTATUS, MCAUSE, and MTVEC. The model implements the basic instruction fetch and decode loop in \step.asl\, handling both compressed and non-compressed instructions, and introduces a structured exception and trap handling mechanism via \exception.asl\ and \trap.asl\. Additionally, it provides helper functions for arithmetic operations (\riscv\_arith.asl\), floating-point operations (\riscv\_fp.asl\), and memory access (\memory.asl\), establishing the foundational behavior for the RISC-V processor model.

pokedex/model/handwritten · high confidence

The Pokedex RISC-V model adds a substantial set of new instructions for the Vector Extension (RVV), covering integer arithmetic (add, sub, min, max, mul, div, rem, shifts), carry/borrow operations (vadc, vsbc, vmadc, vmsbc), and mask manipulation (vcompress, vcpop, vfirst, viota, vmand, vmsbf, vmsif, vmsof). These changes enable the simulator to correctly execute a wider range of vectorized integer and mask-based workloads.

_pokedex/model/extensions/rv\v · high confidence

The simulator now supports loading RISC-V ELF binaries into a configurable memory space defined by KDL configuration files, allowing users to specify SRAM and MMIO regions (including an exit handler) rather than relying on hardcoded defaults. Additionally, a new diff-test subsystem has been added, enabling users to verify the simulator's correctness by comparing its execution trace against a reference Spike emulator log, with results reported as structured JSON diffs.

pokedex/simulator · high confidence

The project has replaced its previous Mill-based build system (build.sc) and Git submodule dependencies with a Nix Flake infrastructure (flake.nix, flake.lock). This change removes the local Git submodules for Chisel and related tools, instead fetching dependencies like Chisel, CIRCT, and Zaozi directly via Nix inputs. The build is now managed through Nix, providing standardized development shells and build targets for the T1 vector processor, its emulator, and configuration generation.

(repo-wide) · high confidence

The ASL model build process has been restructured to use a new buildgen.py script and Ninja build system. This change introduces a Jinja2 template (asl2c.prj.j2) that defines a comprehensive pipeline of transformations for converting ASL code to C, including reachability filtering, type elimination, bit-tuple handling, monomorphization, and constant propagation. A new project.json file explicitly lists external FFI imports (such as memory access and interrupt handling) and exported ASL functions (like Step and ResetState), replacing the previous manual project configuration. Additionally, line info generation is explicitly disabled in the C code generator to prevent confusing GCC diagnostic messages during debugging.

pokedex/model/aslbuild · high confidence

Users can now build the documentation locally using Honkit by following the instructions in the new doc/README.md, which details the required Yarn commands. Additionally, a .markdownlint.json configuration file has been introduced to enforce consistent markdown formatting, with node\_modules excluded from linting via a new .markdownlintignore file to improve CI performance.

doc · high confidence

The Pokedex model now uses a set of new Jinja2 templates to automatically generate self-contained Architecture Specification Language (ASL) code and configuration headers. This includes templates for instruction dispatching (handling both standard and compressed extensions), CSR (Control and Status Register) dispatching with debugger accessors, exception/cause code definitions, and a C-style configuration header (pokedex\_config.h) that exposes profile settings like XLEN, FLEN, VLEN, and enabled extensions. Unimplemented instructions are also handled via generated stubs that trigger debug callbacks. This change shifts the model generation from manual or script-based assembly to a structured, data-driven template approach.

pokedex/model/template · high confidence

This change migrates core Rocket core subsystems—including the DCache, TLB, Frontend, FPU, CSR, PTW, ICache, BTB, and various utility bundles and logic (e.g., DecodeLogic, ImmGen, Replacement policies)—into the new rocketv project structure. This reorganization consolidates these components under the org.chipsalliance.rocketv package, establishing the foundational codebase for the RocketV implementation while maintaining compatibility with existing decoder databases and hardware generation tools.

rocketv/src · high confidence

The omreader module has been replaced with a new implementation that leverages the omlib library. The core OMReader trait now initializes the MLIR context and loads specific dialects (Emit, Firrtl, HW, OM) to parse modules and instantiate classes, while the T1OMReader trait extends this to provide Scala access to the top-level object and JSON serialization capabilities.

omreader · high confidence

The Pokedex model in pokedex/model/csrc now exposes a formal interface (pokedex\_interface.h/c) that replaces the previous vtable-based approach, providing explicit accessors and a redesigned trace protocol for communication with the ASL component. This change introduces a new soft-float wrapper (softfloat\_wrapper.c) that implements IEEE 754 single-precision operations (add, sub, mul, div, sqrt, comparisons, and conversions) using the softfloat library, ensuring correct rounding modes and exception flag handling for RISC-V floating-point instructions.

pokedex/model/csrc · high confidence

The pokedex simulator now exposes a new interface header (pokedex\_interface.h) defining ABI version 2025-12-09. This update introduces a redesigned trace protocol via step\_trace and get\_trace\_buffer to record state write traces, and adds debugger accessors (get\_pc, get\_xreg, get\_freg, get\_vreg, get\_csr) for reading CPU state without side effects. The model export struct also includes get\_description for probing ISA features (xlen, flen, vlen, privilege levels) and debug logging options.

pokedex/simulator/include · high confidence

The single-precision floating-point instruction implementations in the pokedex model have been reorganized into a new file layout. This change introduces dedicated template files (\.j2\) for parameterized operations like FADD\_S, FCVT\_S\_W, FEQ\_S, and FMIN\_S, while moving standalone instructions such as FLW, FSW, and FSQRT\_S into their own explicit files. This restructuring improves the maintainability of the floating-point unit model without altering the functional behavior of the instructions.

_pokedex/model/extensions/rv\f · high confidence

The Nix build system for emulator runs has been restructured to support distinct development and debug features, merging VCS and Verilator run logic into a unified \run-emulator.nix\ module. This change introduces opt-in coverage profiling via \vcs-emu-cover\ (generating assertion reports) and a new \vcs-prof-vcd\ derivation for converting FSDB traces to VCD format. Simulation results are now standardized to \sim\_result.json\, and total cycle counts are automatically replaced with instrumented values from \mmio-event.jsonl\ using a new \calculate-cycle.py\ script. Additionally, the environment has been renamed from \vcs-fhs-env\ to \snps-fhs-env\, and DRAMSim3 configuration paths are now explicitly passed to the emulator.

nix/t1/run · high confidence

The simulation top-level module has been renamed from ClockGen to VerbatimModule. This module now includes a new logging package (\_\_circt\_lib\_logging) that handles RTL event recording via a configurable file descriptor (PRINT\_FD), allowing users to enable or disable event logging through plusargs like +t1\_dev\_rtl\_event\_off and +t1\_dev\_rtl\_event\_path. The module also manages clock generation, reset sequencing, and DPI-C cosimulation initialization with parameters for data length, lane width, vector length, and Spike ISA.

t1emu/vsrc · high confidence

The script build infrastructure has been migrated from the previous system to Mill 0.12.9, introducing a new \build.mill\ configuration that defines \emu\ and \ci\ modules using Scala 3.3.3 and updated dependencies including os-lib 0.10.0, upickle 3.3.1, and requests 0.9.0. This change includes a new Nix derivation (\default.nix\) to build these scripts into standalone JARs and binaries (\t1-helper\ and \ci-helper\), ensuring reproducible builds via a generated \script-lock.nix\ dependency lockfile. Additionally, a \.scalafmt.conf\ file has been added to enforce consistent code formatting with Scala 2.13 dialect for general code and Scala 3 for CI and emulator sources.

script · high confidence

The Spike emulator build now includes patches to relax the VLEN limit (previously capped at 4096 bits), adjust the \vsew \> vlmul \* ELEN\ check to allow \vsew \> ELEN\, and change the reduction order of the \vfredusum.vs\ instruction to use an unordered reduction loop. These changes improve compliance with the RISC-V Vector ISA specification and allow testing configurations with larger vector lengths.

nix/pkgs · high confidence

The stdlib now includes a new GeneralOM class that standardizes the generation, SRAM, and retiming flows for serializable modules, and a new Queue implementation that wraps the DWBB Fifo primitive. The Queue adds 'almost empty' and 'almost full' status ports for entries greater than one, configurable via new parameters, while maintaining backward compatibility for single-entry queues.

stdlib · high confidence

The difftest module has been rewritten in Rust, replacing the previous C++ implementation. This change introduces a new build system using Nix and Cargo, with configuration files for Rust formatting (.rustfmt.toml) and C++ formatting (.clang-format) added to the directory. The module now supports different build targets including DPI libraries for t1emu and t1rocket, as well as an offline simulation checker, all built via the rustPlatform in Nix.

difftest · high confidence

Add RISC-V test environment infrastructure; Add emurt test runtime library; Add smoke test for RISC-V Vector \vsetvli\ instruction; Added IREE-PyTorch matmul test for RISC-V; Added MLIR-based test suite for RISC-V Vector extensions; Added NTT evaluation test suite with scalable test cases; Added PyTorch LeNet end-to-end test; Added PyTorch demo test case for end-to-end MLIR lowering; Added PyTorch matmul E2E test; Added RISC-V Vector test suite with Meson build integration; Added RISC-V compile-stub test infrastructure; Added RISC-V test environment and macro headers; Added RISC-V test suite configuration and build definitions; Added TinyLlama E2E test suite; Added codegen test coverage for RISC-V Vector extensions; Added emurt test suite for simple C program validation; Added formal and simulation tests for arithmetic and crypto modules; Added intrinsic test cases for conv2d, matmul, linear normalization, and softmax; Added performance test for Llama-2 inference on T1; Added test infrastructure and initial MLIR multiplication test for IREE on RISC-V; Added test infrastructure for image processing and memory references; Added verification tests for Berkeley HardFloat submodule; New Meson-based test suite with Nix integration and differential testing; New Nix-based test infrastructure and expanded test suite; New PyTorch E2E test infrastructure and build system; New assembly test suite for RISC-V Vector extensions.

The \dependencies/arithmetic\ and \dependencies/chisel-interface\ directories now include a complete Nix flake setup to manage builds and dependencies. This adds \flake.nix\ and \flake.lock\ files, Nix derivation files for Chisel, softfloat, testfloat, and espresso, and generated mill lockfiles (\arithmetic-mill-lock.nix\, \chisel-mill-lock.nix\) that pin specific versions of Scala libraries (e.g., \mainargs\, \sjson-new\, \fs2\). The \arithmetic\ module also introduces a GitHub Actions CI workflow and a \Makefile\ to build the project using Mill and Nix, while \chisel-interface\ adds build configuration for its \dwbb\, \axi4\, and \jtag\ sub-modules.

dependencies/arithmetic, dependencies/chisel-interface, dependencies/rvdecoderdb · high confidence

The project introduces a new automated workflow for updating dependencies, centered around a new \dependencies/bump.sh\ script that orchestrates version updates for key libraries including Chisel, Chisel-Interface, Arithmetic, HardFloat, Zaozi, and the T1 elaborator through Nix. This change replaces the previous static submodule pointers for Chisel3, ChiselTest, Firrtl, and Treadle with a dynamic fetching process that clones sources, resolves Ivy dependencies, and publishes them locally, as documented in the new \dependencies/docs.md\.

dependencies · high confidence

The repository now manages build dependencies for Chisel, Zaozi, Arithmetic, Chisel Interface, and RVDecoderDB through a new Nix module at dependencies/submodules/default.nix. This change introduces a unified infrastructure using Mill versions 0.12.9 and 1.1.2 to build and publish these components, with specific lock files generated for each project. It also provides automated scripts (passthru.bump) to regenerate these Mill lock files, ensuring consistent dependency resolution across the build system.

dependencies/submodules · high confidence

New dependency lock files have been generated for several Mill-based modules (arithmetic, berkeley-hardfloat, chisel, chisel-interface, rvdecoderdb, and t1). These files pin the exact Maven artifacts and their SHA-256 hashes used by the build system, ensuring reproducible builds by locking versions of dependencies such as Mill 0.12.9, LiHaoyi utilities (fansi, geny, mainargs), and Chisel ecosystem libraries.

dependencies/locks · high confidence

This change introduces the Cargo manifest files (Cargo.toml) and lockfiles (Cargo.lock) for several Rust-based components, including the difftest suite (dpi\_common, dpi\_t1emu, dpi\_t1rocketemu, spike\_rs, t1-sim-checker), the pokedex simulator, the profiler, and the rvdecoderdb sail-impl boat workspace. It also adds the package.json and yarn.lock files for the documentation build system using Honkit. These files establish the dependency graph for the project, specifying versions for key libraries such as clap, tracing, svdpi, and bindgen, and set the Rust edition to 2024 for the new workspaces.

(dependencies) · high confidence

The pokedex-model component now uses a Nix-based build flow, replacing previous methods. This change introduces a new package definition that manages dependencies such as the RISC-V softfloat library, Python, Ninja, and Jinja templates, and configures the build environment to generate C code and libraries via a buildgen script. Users building this model will now rely on Nix for dependency resolution and compilation, with build artifacts like headers and static/shared libraries installed into the standard Nix output directories.

pokedex/model · high confidence

Added design documentation for the T1 vector pipeline, including detailed descriptions of the Lane execution unit (covering its state machine, cross-lane read/write logic, and arithmetic/logic/shift/mul/div units), the Vector Functional Unit (VFU) instruction classification and structure, the Load/Store Unit (LSU) implementation notes, and high-level permutation/mask instruction flow. Also included architectural diagrams (SVG) illustrating the Lane internal structure and register file layout.

t1 · high confidence

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

• First survey — no prior run to compare against. CAI 67.

• Code Health 84
• Architecture 99
• Maturity 70
• Readiness 66
• Security 60

• 300 commits — 263 feature/other, 37 fixes

• pokedex/model — 95 commits
• t1/src — 48 commits
• pokedex/simulator — 33 commits
• pokedex/tests — 20 commits
• .github/designs — 13 commits
• dependencies/locks — 11 commits
• t1zaozi/src — 9 commits
• .github/workflows — 7 commits
• dependencies/submodules — 6 commits
• designs/org.chipsalliance.t1.elaborator.t1rocketemu.TestBench.toml — 5 commits
• nix/pkgs — 4 commits
• nix/t1 — 4 commits
• pokedex/docs — 4 commits
• (root) — 3 commits
• designs/org.chipsalliance.t1.elaborator.t1.T1.toml — 3 commits
• pokedex/codegen — 3 commits
• pokedex/rvopcode — 3 commits
• nix/overlay.nix — 2 commits
• nix/patches — 2 commits
• pokedex/.gitignore — 2 commits

• fix: [nix] fix LLVM compiler-rt cross compilation
• fix: [nix] fix T1 elaborator build after bump
• fix: [nix] fix dramsim3 for cmake 4.0
• fix: [nix] fix ireeturbine nix format
• fix: [pokedex-model] fix makefile dependencies
• fix: [pokedex-model] fix missing PC increasement for zicsr instructions
• fix: [pokedex-model] fix riscv-tests bugs
• fix: [pokedex-model] fix rvv instruction build
• fix: [pokedex] RVV: fix vsetvl/setivli
• fix: [pokedex] RVV: implement fixed-point average add/sub instructions
• fix: [pokedex] difftest : fix difftest for all scalar tests
• fix: [pokedex] fix buildgen and datagen CLI and type error
• fix: [pokedex] fix difftest result output
• fix: [pokedex] fix for multiple tests
• fix: [pokedex] fix general code style issues
• fix: [pokedex] model : fix build
• fix: [rtl] fix aluColSize in zvma.
• fix: [rtl] fix extend
• fix: [rtl] fix free cross token.
• fix: [rtl] fix gather
• …and 280 more

• 0 containers · 5 bounded contexts · 4 dependency edges (baseline)

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

chipsalliance/t1 was measured the same way every project in this corpus was: the same rubric, at a pinned commit, with the result published in full. Point a surveyor at a repository you know and see whether you agree with it.