jeceljr/LivroComputadoresEVideogames

This repository serves as an educational resource for digital logic design and computer architecture, centered around the 'Computadores e Videogames' curriculum. It provides simulation models for fundamental combinational and sequential circuits, alongside complete implementations of classic arcade games like Pong and Soccer on FPGA hardware. Additionally, it defines a custom 16-bit RISC-V-based processor architecture (drv16) and includes tooling for VGA video subsystems and bitstream generation.

The repository now includes a README file describing the 'Computadores e Videogames' book and its practical projects using the Digital simulator, along with a link to the UFABC project page. Additionally, the 'shin\_jamma' project has been added as a Git submodule to integrate the JAMMA arcade interface simulation.

(repo-wide) · high confidence

This change introduces a new set of files in the video directory to support VGA display functionality. It includes a Python script (font2hex.py) to convert 8x16 pixel font data into Intel HEX format, alongside the resulting VGA-8x16.hex font file. Additionally, it adds several digital circuit definitions (.dig files): a timing generator (temporiza.dig), a 12-bit number comparator (compara.dig), and a rectangle detection circuit (retangulo.dig). These components are wired into test harnesses (testeTemporiza.dig, testeQuadradosVGA.dig, testeRetangulosVGA.dig, testeTextoVGA.dig, testeCoresVGA.dig) that simulate VGA signal generation, including horizontal/vertical sync timing and pixel output, with the text test specifically preloading the new font data.

video · high confidence

New circuit design files have been added to the \combinacional\ and \fpga\ directories, providing visual simulation models for various digital logic components. The \combinacional\ folder includes designs for basic gates, adders (\adder.dig\), a 4-bit arithmetic unit (\au4.dig\), a 4x4 multiplier (\mult4x4.dig\), multiplexers (\mux2.dig\, \mux8.dig\), a ROM (\rom4x6.dig\), and switch/relay logic (\switch.dig\, \switchlogic.dig\). The \fpga\ directory introduces a 2x2 FPGA architecture model (\fpga2x2.dig\) utilizing LUT4 and routing components.

combinacional, fpga, sequencial · high confidence

This change introduces the complete digital logic design for a Pong game in the vg1A location. The circuit includes components for ball movement and reflection (bola1d), paddle control (raquete), scorekeeping (placar), and video rendering (pintor, vg). It also provides supporting logic for digit display (digito), rectangle collision detection (retangulo), and timing synchronization (temporiza). The main entry point (sj\_digital) integrates these modules to drive VGA output, effectively implementing the core gameplay mechanics of Pong.

vg1A · high confidence

This location introduces a complete digital logic design for a soccer game, replacing the previous Pong prototype. The changes include the addition of multiple circuit sub-blocks: \jogo.dig\ manages the core game state (ball and player positions, scores); \pintor.dig\ handles the video rendering logic to draw the field, players, ball, and score digits; \raquete.dig\ and \bola1d.dig\ manage player paddle and ball movement physics; \placar.dig\ implements the score counters; and utility modules like \time.dig\ (player positioning), \retangulo.dig\ (collision detection), \compara.dig\ (value comparison), \digito.dig\ (digit display), \ffsr.dig\ (flip-flops), and \temporiza.dig\ (timing/sync) support the main logic. The top-level \sj\_digital.dig\ integrates these components to drive VGA output.

vg1B · high confidence

This change introduces the initial definition for the drv16 processor, a 16-bit RISC-V-based architecture with 16 registers. It includes the assembly macro definitions in drv16.inc for implementing instructions such as arithmetic (ADD, SUB, AND, OR, XOR), logical, jump (JAL, JALR), and load/store operations, along with pseudo-instructions like NOP and LI. The accompanying documentation in drv16.md details the instruction set, noting that while it shares mnemonics with RV32I, it uses a distinct 16-bit encoding scheme that can extend to 32 bits via immediate extension, and explicitly excludes unsigned comparisons, shift instructions, and system calls. A test assembly file (testeAS.S) is also added to verify the assembler's ability to generate binaries for this new architecture.

vg2A · high confidence

The \figuras\ directory now includes new SVG circuit diagrams for an adder, a 4-bit counter, a basic logic block, a 1D ball simulation, and a 4-input AND gate, alongside shell scripts (\allsvg2pdf.sh\, \allsvg2png.sh\) to convert these SVGs to PDF and PNG formats.

figuras · high confidence

The binary file for the Tang Nano 20K device has been updated to a new version (vg1A.fs). This change replaces the previous bitstream, which was reportedly causing reset issues, with a stable configuration generated using Gowin Semiconductor's V1.9.9.03 Education tool for the GW2AR-LV18QN88C8/I7 device.

binarios · high confidence

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

• CAI 41 → 41 (+0.0)
• Rubric changed (rubric-2026.09.15 → rubric-2026.10.1) — scores are not directly comparable.

• Code Health 100 → 100 (+0.0)
• Maturity 39 → 39 (+0.0)
• Readiness 15 → 15 (+0.0)
• Security 100 → 100 (+0.0)

• Documentation: no usage examples (README.md)

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

jeceljr/LivroComputadoresEVideogames was measured the same way every project in this corpus was: the same rubric, at a pinned commit, with the result published in full. Point a surveyor at a repository you know and see whether you agree with it.