schoeberl/chisel-lab

This repository serves as the educational curriculum for a Digital Electronics course, providing structured lab exercises for learning hardware design using the Chisel hardware construction language. It guides students through implementing and verifying digital logic components, such as combinational circuits, sequential state machines, and memory structures, using Scala-based testing frameworks. The system supports FPGA deployment on Basys3 and Nexys A7 boards, offering constraint files and setup documentation to bridge simulation with physical hardware testing.

9 changes.

This period focused on establishing the foundational structure for the Digital Electronics 2 course, including initial lab materials, hardware constraint files, and setup guides for multiple operating systems. The work involved creating starter kits for early labs, such as a Chisel-based LED blinking exercise and combinational circuit implementations, alongside the initial development of a Vending Machine project with corresponding hardware modules and simulation tests.

7 changes.

This period focused on expanding the curriculum with new FPGA lab exercises for seven-segment decoding and multiplexing on the Basys 3 board. Significant effort was also dedicated to improving test coverage by adding ChiselTest-based unit tests for existing hardware modules in Labs 1, 2, and 5.

5 changes.

This period focused on expanding the curriculum with new lab sessions covering sequential circuits, pipelined heap implementations, and UART integration. It also introduced optional testing exercises for hardware verification and added board-specific constraints and initial serial communication modules.

The Vending Machine project now includes a new constraint file (vending-nexys.xdc) for the Digilent Nexys A7-50T/100T FPGA boards, providing pin mappings for switches, LEDs, seven-segment displays, and buttons. A comprehensive README.md has been added to guide users through the design, implementation, and testing of the Chisel-based vending machine, including instructions for simulation and FPGA deployment.

vending · high confidence

New starter files have been added to the lab2 curriculum, providing scaffolded Chisel modules for students to implement specific digital logic functions. These include a 3-bit majority circuit (Majority), a 4-input maximum finder (MaxFinder), a 2-to-1 multiplexer (Mux2), a 2-to-4 decoder (Decoder), and an add/subtract unit (AddSub). Each file contains the module interface and placeholder comments indicating where the student's implementation code should begin.

lab2/src/main · high confidence

Two new Scala source files were added to the lab5 module: CountSevenSeg, which provides a basic seven-segment output with active-low digit enable, and SevenSegDecoder, which accepts a 4-bit switch input and drives the segment lines with inverted logic. Both modules include stubs for user implementation and Verilog generation scripts.

lab5/src/main · high confidence

A new Chisel hardware module named Hello has been introduced in the lab1 source directory, implementing a counter-driven LED blinker that toggles an output pin based on a 100MHz clock cycle. The module includes a main object to generate the corresponding Verilog code, serving as the foundational 'Hello World' hardware example for the first lab exercise.

lab1/src/main · high confidence

Lab 2 now includes exercises for implementing combinational circuits (majority voter, multiplexer, decoder) with provided test suites, along with a README explaining the setup and testing workflow. Additionally, a Xilinx Vivado constraint file (majority.xdc) for the Basys3 board has been added to support optional FPGA synthesis and hardware testing.

lab2 · high confidence

Lab 7 now includes a README explaining how to integrate an external UART component from the ip-contributions library, along with XDC constraint files for the Basys3 and Nexys A7 boards to map the UART TX/RX pins to the correct hardware interfaces.

lab7 · high confidence

This change introduces the core hardware and simulation files for the Lab 6 display exercise. It adds \Display.scala\ as the top-level module that instantiates a \DisplayMultiplexer\ to handle seven-segment display output based on switch inputs. The \DisplayMultiplexer\ module provides the structural framework for the multiplexing logic, with specific implementation sections marked for the student to complete. Additionally, \SevenSegDec.scala\ is added to provide the seven-segment decoding logic, also with placeholders for the required truth table. To support development and verification, a Scala Swing-based GUI simulation (\DisplaySimulation.scala\) is included, allowing users to visually test the display output by entering hex values, alongside a basic Chisel test (\DisplaySpec.scala\) to verify the module instantiation.

lab6/src · high confidence

Added a new SerialPort module in the lab7 source directory that defines a top-level Chisel design with boolean outputs for a UART transmit line (tx) and a blinking LED (led). The module currently drives both outputs to a constant high state, serving as a foundational component for serial communication and visual feedback in the lab environment.

lab7/src · high confidence

Added a new VendingMachine module in Scala that defines the hardware interface for a vending machine, including inputs for coin detection (2 and 5 unit coins) and buy commands, and outputs for can release, alarm, and 7-segment display control. The module currently implements basic logic where the alarm triggers on a 2-unit coin, the can releases on a 5-unit coin, and the display shows a fixed pattern, with Verilog generation enabled for simulation.

vending/src/main · high confidence

This change introduces the initial repository content for the Digital Electronics 2 course at DTU, providing the foundational lab structure and documentation. It adds comprehensive setup guides for Ubuntu, Windows 10, and macOS (including Apple Silicon via MacM1.md), a FAQ addressing common Chisel and Vivado errors, and the specific hardware constraint files (Basys3\_Master.xdc and Nexys-A7-Master.xdc) required for programming the target FPGA boards. The entry also includes the initial lab exercises (starting with Lab 1: Hello World) and the necessary tool configuration scripts (7series.txt) for OpenOCD-based FPGA programming.

(repo-wide) · high confidence

An optional lab has been added that challenges users to write tests to distinguish between two vending machine implementations (VendingA and VendingB), one of which contains a logic error. The lab provides Scala test scaffolding using ChiselTest and Verilator, along with the corresponding Verilog black-box models for both implementations, allowing students to practice hardware verification by identifying the faulty behavior.

lab10 · high confidence

This change introduces the complete starter kit for Lab 1, which guides users through building a 'Hello World' Chisel design that blinks an LED on an FPGA. The addition includes two XDC constraint files (Basys3Hello.xdc and NexsysA7Hello.xdc) defining pin mappings for Basys3 and Nexys A7 boards, a comprehensive README.md with step-by-step instructions for setting up IntelliJ, compiling with sbt, and synthesizing with Vivado, and the underlying Chisel source code (referenced in the README as Hello.scala) that generates the Verilog for the blinking LED.

lab1 · high confidence

This update introduces the third lab session, which guides users through creating and using Chisel components (modules) and building small sequential circuits. The lab includes exercises for instantiating a 2:1 multiplexer (Mux2), constructing a 4:1 multiplexer (Mux4) from Mux2 instances, and implementing sequential logic such as a two-clock-cycle delay, a free-running 4-bit counter (Count15), a counter with a limit (Count6), and an accumulator (Accu). The provided Scala source files contain the module skeletons and IO definitions, while the corresponding test specifications (using ChiselTest) verify the expected behavior of each component.

lab3 · high confidence

Lab 4 now includes a complete, pipelined k-ary heap implementation in Scala/Chisel, composed of modular components: HeapControl (state machine for insert/remove), Fetcher (fetches parent/children from memory), MaxFinder (identifies largest child), Heapifier (manages swap logic), Swapper (performs memory writes), HeapMemory (banked SyncReadMem storage), and supporting types in the heap package. A test scaffold (HeapTest.scala) is provided with stubbed tests for heap properties. Additionally, a broken 5:1 multiplexer (Mux5.scala) is added as an exercise, accompanied by an empty test file (Mux5Test.scala) for students to fix.

lab4/src · high confidence

A new lab exercise has been introduced for the seven-segment decoder and test circuit. This includes a README with instructions for implementing the decoder logic, running Chisel tests, and synthesizing the design for the Basys 3 FPGA. The update also adds two XDC constraint files (\sevenseg.xdc\ and \sevenseg-cnt.xdc\) defining pin mappings for the seven-segment display, switches, and reset button, enabling students to verify their hardware implementation.

lab5 · high confidence

A new lab exercise has been added for the Basys 3 FPGA board, requiring students to build a synchronous Chisel circuit that displays four hexadecimal digits on the time-multiplexed seven-segment display. The lab provides a pin definition file (display.xdc) mapping the segment and digit-anode signals to the FPGA pins, along with instructions to reuse the previous SevenSegDec module and implement a 1 kHz refresh rate using a 100 MHz clock.

lab6 · high confidence

Added Basys3 board simulation and unit tests for the vending machine; Added ChiselTest-based unit tests for lab2 hardware modules; Added simulation test for LED blinking behavior; Added test suites for SevenSegDecoder and SevenSegCount.

The build.sbt files for labs 1-7 and the vending project have been updated to use Scala 2.13.14 and Chisel 3.6.1 (along with ChiselTest 0.6.2), replacing the previous Chisel 3.5/3.4 configurations. Additionally, the lab6 and vending projects now explicitly include the scala-swing 3.0.0 dependency, while lab7 includes the ip-contributions 0.6.1 library.

(dependencies) · high confidence

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

• First survey — no prior run to compare against. CAI 54.

• Code Health 100
• Architecture 100
• Maturity 39
• Readiness 36
• Security 100

• 255 commits — 246 feature/other, 9 fixes

• (root) — 81 commits
• (repo) — 16 commits
• vending/README.md — 16 commits
• lab4/src — 11 commits
• lab5/README.md — 10 commits
• lab2/src — 9 commits
• lab4/README.md — 9 commits
• lab5/src — 9 commits
• lab8/src — 9 commits
• lab1/build.sbt — 7 commits
• lab2/README.md — 7 commits
• labx/src — 7 commits
• vending/src — 7 commits
• lab1/README.md — 6 commits
• lab3/src — 4 commits
• lab6/README.md — 4 commits
• lab6/src — 4 commits
• lab7/README.md — 4 commits
• labx/images — 4 commits
• lab10/src — 3 commits

• fix: Fix LED in master XDC for NexysA7
• fix: Fix some warnings
• fix: Update Chisel version and minor fix
• fix: lab11: fix README
• fix: lab1: final fixes
• fix: lab3: fix tester
• fix: lab7: fix README
• fix: lab7: fix UART pin assignement for Nexus
• fix: vending: fix lab week
• change: 7-segment exercise altered to conform with board
• change: 7segment display and test with waveforms
• change: A useful text for the demo
• change: Add explicit scala-swing dependency to vending machine project
• change: Add heap test to Lab 4
• change: Add links to git clients and tutorials
• change: Add support for the Nexsy A7 board
• change: Add the Nexus A7 target
• change: Added Windows 10 in Setup.md
• change: Back to 3.6 to generate Verilog files, not SV
• change: Better link to Chisel book in README
• …and 235 more

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

schoeberl/chisel-lab was measured the same way every project in this corpus was: the same rubric, at a pinned commit, with the result published in full. Point a surveyor at a repository you know and see whether you agree with it.