SpinalHDL/NaxRiscv

NaxRiscv is a configurable, plugin-based RISC-V processor core implemented in Scala using the SpinalHDL hardware description language. It provides a modular architecture for generating RTL that supports RV32/RV64, floating-point extensions, and various performance features like branch prediction and multi-issue execution. The system includes comprehensive tooling for simulation via Verilator and Spike, ASIC synthesis targeting Sky130, and integration with LiteX SoC frameworks, along with JTAG debug support for hardware and simulation environments.

14 changes.

This period established the foundational infrastructure for the NaxRiscv RISC-V processor, including project scaffolding, build tooling, and external dependency integration. It introduced a modular, plugin-based Scala framework for generating the core, defining the multi-stage frontend pipeline, and implementing execution units for integer, floating-point, and memory operations.

10 changes.

This period focused on expanding the NaxRISCv core with a pipelined FPU supporting RVF and RVD extensions, alongside new commit and performance monitoring plugins. Significant work was also dedicated to establishing comprehensive hardware debug capabilities through embedded JTAG support, OpenOCD configuration, and detailed CPU state tracing for simulation and synthesis.

8 changes.

This period focused on expanding the NaxRiscv project with comprehensive SoC simulation and hardware generation capabilities, including LiteX and ASIC (Sky130) platform support. Significant effort was dedicated to building robust simulation infrastructure, featuring ELF parsing, C++ Spike integration, and multi-threaded testing. The work also established automated CI pipelines and regression test generation to streamline development and verification workflows.

The ASIC platform generation tool now includes a new Sky130 PDK target, allowing users to generate Verilog with SRAM macros tailored for the Sky130 process via the \--sky130-ram\ flag. The generator exposes several command-line options to customize the RISC-V core: \--no-lsu\ disables the Load/Store Unit (and MMU), \--io-ff\ enables flip-flop outputs, \--no-rf-latch-ram\ disables latch-based register file RAM, and \--bb-comb-ram\ blackboxes combinational RAM. Additionally, the \--regfile-fake-ratio\ parameter allows tuning the register file implementation, and the Sky130 target automatically configures specific cache, branch predictor, and LSU sizes optimized for that technology.

src/main/scala/naxriscv/platform/asic · high confidence

Added new OpenOCD configuration files to support debugging the NaxRISCV core on Digilent Nexys Video hardware and in simulation environments. The \digilent\_nexys\_video.tcl\ script configures the FTDI adapter for the specific board, while \naxriscv\_jtag.tcl\ sets up a standard JTAG chain for one or more CPU cores. Additionally, \naxriscv\_sim.tcl\ provides a TCP-based JTAG interface for simulation, and both \naxriscv\_jtag\_tunneled.tcl\ and \naxriscv\_sim\_tunneled.tcl\ enable BSCAN tunneling for accessing the RISC-V core through a JTAG chain.

src/main/tcl · high confidence

The NaxRiscv debug module now includes an EmbeddedJtagPlugin that integrates the RISC-V Debug Module (DM) with a Debug Transport Module (DTM) via DMI. This change enables hardware debug capabilities, allowing external tools like OpenOCD to read/write registers and memory over JTAG. The plugin supports both direct JTAG tap connections and JTAG tunneling, and connects the debug bus to the processor's privileged bus to handle hart debug mode, exceptions, and reset/halt requests.

src/main/scala/naxriscv/debug · high confidence

New plugin-based adapters have been introduced to translate the LSU's internal native bus into standard AMBA interfaces. The DataCacheAxi4 adapter converts the data cache memory interface to AXI4, while the LsuPeripheralAxiLite4 adapter exposes the LSU's peripheral bus as an AXI-Lite interface. The AXI-Lite adapter includes configurable pipelining (register stages) for both command and response channels to allow timing optimization, and applies standard AXI specification renaming to ensure protocol compliance.

src/main/scala/naxriscv/lsu · high confidence

Users can now load RISC-V ELF binaries directly into simulation memory via the new \Elf\ class in \spinal.lib.misc\, which utilizes the \net.fornwall.jelf\ library to parse sections and symbols. A new \Playground\ object in \riscv.model\ demonstrates integration with the C++ Spike ISA simulator, compiling and linking native model code to interact with the simulation. Additionally, a \MultithreadedFunSuite\ has been added to \spinal.lib.misc.test\ to allow tests to run concurrently across multiple threads while safely capturing and merging console output.

src/main/scala/spinal · high confidence

Introduced two new Java classes, \riscv.model.Backeup\ and \riscv.model.Model\, which serve as Java Native Interface (JNI) bindings for external C++ components. \Model\ provides methods to instantiate and delete a native RISC-V model by loading the shared library located at \ext/rvls/build/apps/rvls\, while \Backeup\ offers similar native handle management (including a stub method) by loading \src/main/cpp/riscv/model/model.so\. These classes enable the Java application to interact with the underlying C++ simulation logic.

src/main/java · high confidence

A new Verilog module, RamXilinx.v, has been added to the Xilinx directory. This module implements a RAM with one write port and one read port, supporting configurable word counts, widths, and clock crossing. It specifically includes logic for write masking, allowing selective updates to parts of a word during a write operation, and handles read-under-write behavior based on configuration parameters.

src/main/verilog · high confidence

This change introduces a collection of experimental Scala scripts within the \naxriscv.sandbox\ package to support development and validation. \FpuRandomGen\ generates randomized RISC-V assembly sequences for FPU instruction testing, while \Play.scala\ provides simple hardware simulation snippets and GCC target string generation. \Stats.scala\ offers statistical analysis for cache conflict probabilities and includes synthesis benchmarks for various logic components on Xilinx Artix-7. Additionally, \Integration.scala\ files in \cam\, \cam2\, \matrix\, \matrix2\, and \matrix3\ subdirectories implement and benchmark hardware slot selectors and wait tables, and \Demo.scala\ demonstrates pipeline and thread simulation features.

src/main/scala/naxriscv/sandbox · high confidence

Added the OpenLane configuration files for the 'nax' design, including a Tcl config script and a macro placement file. The configuration sets up synthesis with the SYNTH\_AUTONAME parameter enabled to assist with timing analysis, defines a 3600x3600 die area with 20% core utilization, and specifies fixed placements for four specific memory macros (FetchCachePlugin, BtbPlugin, and GSharePlugin). It also includes workarounds for known OpenLane issues regarding power distribution network halos and combinational loops.

src/main/openlane · high confidence

The repository is initialized with essential configuration files to support development and simulation. A .gitignore file is added to exclude build artifacts, IDE settings, and temporary files. Submodules are configured via .gitmodules to pull in external dependencies including NaxSoftware, riscv-isa-sim, rvls, and SpinalHDL. A Makefile is introduced to manage the build process, defining targets for installing a RISC-V toolchain, Verilator, and other dependencies, as well as generating RTL and running simulations. Additionally, a .jvmopts file sets JVM memory limits for the build system, and a reuse.sh script is added to manage SPDX license headers across source files.

(repo-wide) · high confidence

Adds a new NaxSoc system-on-chip implementation for the LiteX platform, providing a configurable SoC builder that supports multiple RISC-V cores, an optional L2 cache, AXI DMA, and standard peripherals (CLint, PLIC). The integration includes a reset controller to manage timing constraints, isolated DMA handling, and configurable memory regions mapped via AXI4 and AXI-Lite bridges, enabling users to generate complex SoC designs with debug (JTAG) and monitoring capabilities.

src/main/scala/naxriscv/platform/litex · high confidence

This change introduces the foundational decoding logic and resource specifications for the NaxRiscv processor core. It adds \RegFile.scala\ to define the integer and floating-point register files, including their architectural sizes and resource requirements for various instruction types (e.g., TypeR, TypeI, TypeB). It also adds \Rvi.scala\ and \Rvfd.scala\, which contain the complete set of opcode definitions for the RV32I base integer instruction set (including arithmetic, logical, load/store, branch, jump, and atomic operations) and the RVD floating-point extension (including single/double precision arithmetic, conversions, and memory access). These files establish the mapping between RISC-V opcodes and the internal pipeline resources needed for execution.

src/main/scala/naxriscv/riscv · high confidence

The NaxRiscv RISC-V processor core is now generated via a new Scala-based build system. The \Gen.scala\ file introduces a plugin-based architecture where the core's features (such as MMU, FPU, JTAG, and branch prediction) are composed by instantiating specific plugins like \MmuPlugin\, \GSharePlugin\, and \Lsu2Plugin\. The \Config\ object provides a high-level API for users to define core parameters, including XLEN (32/64-bit), support for RVC/RVF/RVD extensions, cache sizes, and pipeline depth. Supporting files \Parameters.scala\ and \Tweek.scala\ define global stageables (like PC width and XLEN) and provide utility functions to tune execution unit write-back stages, allowing users to customize timing and resource usage without modifying the core logic directly.

src/main/scala/naxriscv · high confidence

Added a suite of shell scripts in the \ci/\ directory to automate the setup of the NaxRiscv development environment. These scripts handle cloning submodules (\clone-submodules.sh\), installing dependencies like Verilator, OpenJDK, and SBT, and building the Spike simulator with its required libraries (ELFIO, SDL) and the RVLS tool. This centralizes the build process, ensuring consistent installation of Spike as a shared library and simplifying the local setup for developers.

ci · high confidence

Added SocDemo, a configurable multi-core SoC model for simulation, and SocSim, a command-line simulation harness. SocDemo allows users to configure CPU counts, XLEN, and optional RVC, floating-point, and double-precision extensions, with support for L2 cache and ASIC-specific optimizations. SocSim provides a flexible testing environment with CLI options to load ELF/binary images, enable wave tracing, disable the L2 cache, and run dual-sim lockstep verification, enabling users to boot Linux or run bare-metal benchmarks on the simulated hardware.

src/main/scala/naxriscv/platform/tilelinkdemo · high confidence

This change introduces four new plugins in the NaxRISCv misc module to enhance debugging, performance monitoring, and CSR access. CommitDebugFilterPlugin adds a configurable filter to track commit events, while PerfCsrPlugin exposes hardware performance counters for instruction/data cache refills, writebacks, and waits via specific CSR addresses. CsrRamPlugin provides a prioritized, pipelined RAM service for CSR read/write operations, allowing other components to host CSR data. CommitPlugin implements the core commit logic with support for multiple reschedule ports, trap handling, and ROB management, forming the basis for the commit stage's behavior.

src/main/scala/naxriscv/misc · high confidence

The execute stage now includes dedicated plugins for core RISC-V operations: IntAluPlugin handles integer ALU and shift instructions, BranchPlugin manages branch and jump logic with prediction context support, LoadPlugin and AguPlugin (Address Generation Unit) handle load/store and atomic memory operations (including LR/SC and AMOs), DivPlugin implements radix-4 division and remainder, MulPlugin provides pipelined multiplication with configurable ASIC/FPGA optimizations, CsrAccessPlugin manages CSR read/write with trap handling, EnvCallPlugin implements environment calls, breaks, and fence instructions, and CsrTracer adds monitoring for CSR writes. These plugins replace the previous monolithic execution logic with a modular, stage-configurable architecture that supports dual-issue and 64-bit operations.

src/main/scala/naxriscv/execute · high confidence

This change introduces several new core components for the NaxRiscv processor. It adds \MultiportRam.scala\ with \RamAsyncMwXor\, \RamAsyncMwMux\, \RamSyncMwXor\, and \RamMr\ to support multi-port RAM implementations using XOR or MUX-based storage strategies. It introduces \ExecutionUnitBase.scala\ as a base class for execution units, providing a framework for defining pipelines, register file access, and write-back logic. Additionally, it adds the FPU execution logic, including \FpuCore.scala\ for the main floating-point pipeline, \FpuDiv.scala\ for division, and \FpuSqrt.scala\ for square root operations, along with their associated interfaces and parameters.

repository · high confidence

The NaxRiscv core now includes a new, fully pipelined Floating Point Unit (FPU) located in src/main/scala/naxriscv/execute/fpu. This implementation adds support for the RVF (single-precision) and RVD (double-precision) extensions, enabling hardware acceleration for floating-point arithmetic including add, subtract, multiply, divide, square root, fused multiply-add (FMA), and integer-to-float/float-to-integer conversions. The FPU is structured with dedicated execution units for float and integer operations, a pipelined multiplier, and a write-back stage that handles register file updates, ROB completion, and floating-point status flag management. It integrates with the core's pipeline via unschedule signals and supports configurable rounding modes via the FCSR CSR.

src/main/scala/naxriscv/execute/fpu · high confidence

This change introduces a suite of new components in the \naxriscv.platform\ package to support advanced simulation and integration workflows. \TilelinkNaxRiscvFiber\ provides a configurable RISC-V core implementation over TileLink with support for RVC and floating-point extensions, while \NaxRiscvBmbGenerator\ offers a parallel implementation for BMB bus interconnects. To facilitate debugging and verification, \NaxriscvProbe\ and \Tracer\ add detailed CPU state tracing (including register, CSR, and memory access logging) with backends for file output and JNI integration with Spike. Additionally, \PeripheralEmulator\ enables Linux boot simulation by emulating specific peripherals (like CLINT and interrupt controllers) and handling I/O scheduling, and \SynthesisTests\ provides a benchmarking framework for RTL synthesis.

src/main/scala/naxriscv/platform · high confidence

The NaxRiscv utilities module introduces a new plugin-based architecture for hardware construction, featuring a \Framework\ that manages \Service\ and \Plugin\ components through distinct configuration, early, and late elaboration phases. This includes a \DataBase\ for scoped parameter storage and a \DocPlugin\ for generating C headers. Additionally, an \XilinxDebug\ plugin is added to automatically expose internal pipeline signals (such as cache, LSU, MMU, and commit stages) as debug probes for Xilinx hardware, and a \DebugScratchCsrPlugin\ provides configurable scratchpad CSRs for debugging.

src/main/scala/naxriscv/utilities · high confidence

The frontend has been restructured into a multi-stage pipeline (decompressed, decoded, serialized, allocated, dispatch) to improve timing and dependency tracking. A new DispatchPlugin introduces an issue queue that handles instruction dispatch, fence ordering (fenceYounger/fenceOlder), and static latency wakeups, while a new RfAllocationPlugin manages physical register file allocation with pessimistic ready signals and zero-register protection. The DecoderPlugin now inserts architectural register IDs directly into the pipeline, and the FrontendPlugin orchestrates the new stage connections, allowing for better resource management and relaxed timing constraints across the core.

src/main/scala/naxriscv/frontend · high confidence

The branch prediction logic in the frontend has been restructured into distinct, reusable plugins: BtbPlugin (Branch Target Buffer), GSharePlugin (global history predictor), and DecoderPredictionPlugin (decoder-level prediction and Return Address Stack management). This change introduces specific behavioral improvements: the Return Address Stack (RAS) now heals its pointer on commit rescheduling to maintain correctness during mispredictions, and the GShare predictor now implements up/down counters for more accurate branch direction learning. Additionally, the BTB has been updated to learn PC targets instead of next PCs and uses a read-first policy to avoid hazards, while the decoder prediction plugin now integrates conditional branch predictions from the fetch stage to correct history.

src/main/scala/naxriscv/prediction · high confidence

The fetch frontend has been restructured to introduce a dedicated AlignerPlugin that handles instruction alignment and prediction sanity checks, replacing previous inline logic. This plugin now uses native fetch stages for combinatorial chaining and includes a prediction sanity mechanism to prevent bad prediction aliasing. Additionally, new FetchAxi4 and FetchPlugin components have been added to provide bus width adapters, translating internal fetch interfaces into AXI4 and AXI-Lite protocols for memory and peripheral access, while the FetchPlugin centralizes pipeline stage management and fetch ID tracking.

src/main/scala/naxriscv/fetch · high confidence

Added NaxRiscv regression test infrastructure; Added license file for Konata test asset; Added test generation script for RISC-V regression tests; Added test infrastructure for ELF loading, framebuffer, JTAG, and block devices; Initial test infrastructure for NaxRiscv simulator.

The project now uses an SBT build file (build.sbt) to define the NaxRiscv build, targeting Scala 2.12.18 and version 2.0.0. It configures the SpinalHDL IDSL plugin from a local submodule (ext/SpinalHDL) and includes dependencies for ScalaTest 3.2.17, SnakeYAML 1.8, and the jelf library 0.7.0.

(dependencies) · high confidence

The repository now includes four new Git submodules under the ext/ directory: NaxSoftware, SpinalHDL, riscv-isa-sim, and rvls. These additions provide the necessary external dependencies for RISC-V software simulation and hardware description, enabling the project to leverage these tools for testing and development workflows.

ext · high confidence

A license file (assets/pipeline.png.license) has been added to the assets directory, explicitly stating that the pipeline.png image is licensed under CC0-1.0 with copyright held by Everybody since 2023.

assets · high confidence

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

• First survey — no prior run to compare against. CAI 61.

• Code Health 90
• Architecture 97
• Maturity 50
• Readiness 50
• Security 93

• 300 commits — 224 feature/other, 76 fixes

• src/main — 161 commits
• src/test — 29 commits
• (repo) — 28 commits
• (root) — 22 commits
• .github/workflows — 19 commits
• ext/NaxSoftware — 12 commits
• ci/install-verilator.sh — 7 commits
• ext/SpinalHDL — 7 commits
• ci/install-libsdl-elfio-spikespinalhdl.sh — 3 commits
• ext/rvls — 3 commits
• ci/build_spike_rvls.sh — 2 commits
• ci/clone-submodules.sh — 2 commits
• ext/riscv-isa-sim — 2 commits
• ci/install-elfio.sh — 1 commit
• ci/install-openjdk.sh — 1 commit
• ci/install-riscv-gnu-toolchain.sh — 1 commit

• fix: Add latch based register file and fix Lsu2 not sharing regfile write port
• fix: Added a Python script that generates all the necessary Makefiles to run regression tests with RVLS.
• fix: Added a Scala file to launch regression tests with RVLS, including configuration setup, test execution, and result reporting
• fix: Added regression test for RVLS in GitHub Actions workflow. Updated scala.yml to include a new RVLS-specific test step and added test-rvls function in tools.sh.
• fix: Fix #101
• fix: Fix #104
• fix: Fix #105
• fix: Fix #106 #103 implement tsr, tw, tvm (tw as dummy)
• fix: Fix #112 mstatus.tw
• fix: Fix #112 mstatus.tw
• fix: Fix #112 mstatus.tw
• fix: Fix #121
• fix: Fix #121
• fix: Fix #148 FPU -> int writeback when x0 is targeted
• fix: Fix #149
• fix: Fix #158 (fpu write to integer x0 will not wakeup rob anymore
• fix: Fix #57 litex memory mapping at offset 0
• fix: Fix LR pulling lockup Fix coherent-less configs generation
• fix: Fix MTVEC STVEC mode legality #153
• fix: Fix MulSpliter
• …and 280 more

• 0 containers · 1 bounded contexts · 0 dependency edges (baseline)

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

SpinalHDL/NaxRiscv was measured the same way every project in this corpus was: the same rubric, at a pinned commit, with the result published in full. Point a surveyor at a repository you know and see whether you agree with it.