SpinalHDL/VexiiRiscv

VexiiRiscv is a configurable RISC-V processor generator built on the SpinalHDL framework, allowing users to synthesize custom CPU cores with varying pipeline architectures, cache hierarchies, and memory management units. It provides a plugin-based architecture for integrating standard and custom instruction set extensions, such as floating-point, bit manipulation, and cryptographic operations, alongside support for hypervisor and interrupt controller features. The system includes comprehensive tooling for simulation, verification, and SoC integration, enabling the generation of hardware descriptions for diverse embedded environments.

25 changes.

This period established the VexiiRiscv project by configuring the build infrastructure with Mill and SBT, integrating external dependencies, and initializing the Git repository. It introduced the foundational plugin-based architecture for the RISC-V processor generator, implementing core subsystems such as the instruction fetch, decode, execution, and memory management units. The work also included expanding ISA support with various extensions and developing comprehensive testing and simulation frameworks to validate the new hardware designs.

11 changes.

This period focused on expanding the VexiiRiscv ecosystem by introducing a Tilelink-based SoC integration layer, a new L1 data cache, and a full-featured floating-point unit. Significant effort was also directed toward enabling Linux support through LiteX Buildroot and Debian configurations, alongside comprehensive debugging infrastructure including OpenOCD scripts and Docker environments.

This change introduces a new Buildroot external tree for LiteX-based SoCs, providing a complete configuration to build a Linux root filesystem for the VexRiscv CPU. It includes board-specific kernel configurations for both a basic LiteX SoC and a variant with USB host support, along with rootfs overlays that configure the init system, shell environment, and X11 display settings. The tree also adds a custom Buildroot package for an optimized Dhrystone benchmark and patches for Chocolate Doom to enable unrolled rendering and FPS display on the target hardware.

doc/litex/buildroot · high confidence

The project now includes a Mill build system alongside the existing SBT setup. New files such as \project/Version.mill\ and \project/package.mill\ have been added to support Mill, while \project/Version.scala\ and \project/plugins.sbt\ define the SBT configuration, including the \sbt-assembly\ and \sbt-repeat\ plugins. The SBT version has been set to 1.10.0 in \project/build.properties\, and \project/version.conf\ specifies supported Scala compiler versions 2.12.18 and 2.13.12.

project · high confidence

Added a new README guide and a Linux kernel configuration file to the project documentation. The README provides step-by-step instructions for setting up the build environment, installing dependencies (including RISC-V toolchains and Litex), creating a Debian root filesystem, compiling the Linux kernel, and generating/loading hardware images for the VexiiRiscv CPU on the Digilent Nexys Video board. The included linux.config file provides the specific kernel configuration used for this Debian build.

doc/litex/debian · high confidence

A new Play.scala file was added to the sandbox directory containing experimental code for the VexiiRiscv processor. This includes an EventCounterPlugin and EventSourcePlugin demonstrating how to use SpinalHDL's FiberPlugin mechanism to coordinate elaboration phases and aggregate events across multiple hardware lanes. It also introduces AlphaPlugin and BetaPlugin examples that utilize the SpinalHDL Database API for sharing configuration parameters between plugins during the setup phase.

src/main/scala/vexiiriscv/sandbox · high confidence

This change introduces the core memory management hardware components for the VexiiRiscv processor. It adds MmuPlugin to handle first-stage virtual-to-physical address translation (supporting sv32 and sv39 page tables with TLB, ASID, and guest checks), PmpPlugin to implement Physical Memory Protection (TOR and NAPOT regions), and ShadowMmuPlugin for second-stage hypervisor address translation. It also includes PmaLogic for physical memory attribute checking, StaticTranslationPlugin for MMU-less configurations, and TranslatedDBusAccessPlugin to manage bus transactions through the translation stages.

src/main/scala/vexiiriscv/memory · high confidence

The RISC-V CPU core now supports a significantly broader set of instruction set extensions, including the Hypervisor extension (RVH) with guest physical memory management instructions (HLV/HSV), the Zkn scalar crypto extension (AES, SHA2/3, SM3/SM4), and the Zba/Zbb/Zbs bitmanip extensions. Additionally, the core implements the RVC (compressed instructions) decompressor, full floating-point arithmetic (RVF/RVD), and atomic operations (RVA), providing a more complete and standards-compliant RISC-V implementation for complex software environments.

src/main/scala/vexiiriscv/riscv · high confidence

Adds a Dockerfile and supporting scripts to create a containerized development environment for RISC-V simulation. The image installs necessary build tools (OpenJDK 21, SBT, Verilator, ELFIO), sets up a graphical desktop environment (Xvfb, VNC, XFCE4) for running the Konata viewer, and includes scripts to configure user permissions, patch the fesvr library, and build the VexiiRiscv project.

docker · high confidence

This change introduces the foundational structure for the VexiiRiscv project, including a new README with feature overviews and getting-started instructions, a Mill build definition (build.mill) replacing or supplementing previous build systems, and a Dockerfile for containerized development. It also adds a .gitignore to exclude build artifacts and IDE files, configures JVM options for memory and stack size, and initializes git submodules for external dependencies like SpinalHDL and NaxSoftware. A helper script (run\_docker.sh) is provided to launch the Docker environment with VNC access.

(repo-wide) · high confidence

This change introduces the VexiiRiscv project, a configurable RISC-V processor generator built on the SpinalHDL framework. It provides a plugin-based architecture allowing users to generate custom CPU cores by selecting from a wide range of supported RISC-V extensions (including base, M, A, F, D, C, and various Z extensions) and configuring features such as branch prediction (BTB, GShare, RAS), cache hierarchies (L1/L2), MMU, FPU, and bus interfaces (AXI4, Wishbone, TileLink). The generator exposes command-line options to define memory regions, physical address widths, and specific implementation parameters, enabling the creation of diverse processor configurations from single-issue to dual-issue pipelines.

src/main/scala/vexiiriscv · high confidence

This change introduces the MicroSoc system-on-chip, a configurable RISC-V SoC built on the Tilelink bus. It includes a VexiiRiscv CPU, RAM, CLINT, PLIC, UART, and an optional SPI Flash controller with XIP support. Users can enable debug capabilities via a JTAG tap and a dedicated debug sysbus, and can instantiate a demo peripheral with configurable LED and button counts. A BSP generator is provided to automatically create a C header with peripheral memory addresses, and the design supports simulation with OpenOCD and ELF loading.

src/main/scala/vexiiriscv/soc/micro · high confidence

The processor now supports a Custom Functional Unit (CFU) architecture, allowing users to implement custom hardware instructions outside the core CPU via a stream-based interface. This change introduces the \CfuBus\ protocol for command/response communication and the \CfuPlugin\ which integrates custom instruction decoding, register access (RS1/RS2 or immediate), and CSR management (including state index and status flags) into the execution pipeline. Users can now define custom instruction encodings and offload specific computations to external hardware logic connected through this bus.

src/main/scala/vexiiriscv/execute/cfu · high confidence

Added a new \Elf\ class in \src/main/scala/spinal/lib/misc/Elf.scala\ that provides utilities for parsing ELF files, locating symbols, and loading program data into simulation memory. This enables users to initialize RAM with binary content from ELF files during hardware simulation and map symbol addresses for debugging or analysis tools like the included \ElfMapper\.

src/main/scala/spinal/lib/misc · high confidence

The memory subsystem now includes a configurable, non-blocking L1 data cache (LsuL1Plugin) and a dedicated cacheless LSU (LsuCachelessPlugin) for uncached and IO memory accesses. The L1 cache supports coherency probes, write-back, and bypass, while the cacheless path handles atomic instructions and IO transactions. Both implementations are connected to the system interconnect via new bridge plugins that translate the internal LSU buses to TileLink, AXI4, and Wishbone protocols, enabling flexible SoC integration.

src/main/scala/vexiiriscv/execute/lsu · high confidence

The Litex SoC simulation environment has been restructured into dedicated source files (Soc.scala, SocSim.scala, VgaDisplaySim.scala) to support advanced debugging and verification workflows. Users can now run simulations with a graphical VGA output monitor via the new VgaDisplaySim tool, which renders video signals in a GUI window. The simulation harness (SocSim) now supports dual-sim execution for self-testing, allows specifying pass/fail symbols to automatically terminate on test results, and enables peripheral simulation via the --sim-peripheral flag. Additionally, the SoC configuration exposes command-line options for multi-core support, L2 cache self-flush, AXI3 interfaces, and custom device memory mappings.

src/main/scala/vexiiriscv/soc/litex · high confidence

Added a suite of OpenOCD Tcl configuration scripts to support development, simulation, and hardware debugging workflows. The new \dev.tcl\, \dev\_rv64gc.tcl\, and \vexiiriscv\_jtag.tcl\ scripts introduce support for multi-core (HART) debugging by reading the \HART\_COUNT\ environment variable to iterate over and resume multiple CPU targets. Additional scripts provide specific configurations for Digilent Nexys Video and FT2232H breakout hardware interfaces, simulation via remote bitbang (\vexiiriscv\_sim.tcl\), and BSCAN tunneling for JTAG (\vexiiriscv\_jtag\_tunneled.tcl\). Utility scripts \prefetch\_enable.tcl\ and \prefetch\_disable.tcl\ allow users to toggle the instruction prefetcher via register manipulation, and \trace.tcl\ provides a basic instruction trace capture capability.

src/main/tcl · high confidence

A new integration component, TilelinkVexiiRiscvFiber, has been added to the SoC layer to bridge the VexiiRiscv CPU core with the Tilelink bus fabric. This component manages the connection of instruction and data buses, integrates with the PrivilegedPlugin for standard interrupts (timer, software, external), and adds support for IMSIC (Interrupt Mailbox and Source Interface Controller) and APLIC (Advanced Platform Level Interrupt Controller) interrupt routing. It also handles the automatic wrapping of CPU plugins (Fetch and LSU) with their corresponding Tilelink-compatible versions and configures memory regions for PMA (Physical Memory Attributes).

src/main/scala/vexiiriscv/soc · high confidence

The floating-point unit in the execute stage has been replaced with a new implementation that supports the full RISC-V F and D extensions. This adds hardware support for floating-point addition, subtraction, multiplication, fused multiply-add (FMA), division, square root, and conversions between floating-point and integer formats. It also includes comparison operations (min/max, less/equal), sign manipulation, and the FCLASS classification instruction. The new FPU manages rounding modes, exception flags (NV, DZ, OF, UF, NX), and handles special cases like subnormals, infinities, and NaNs according to the IEEE 754 standard.

src/main/scala/vexiiriscv/execute/fpu · high confidence

The prediction module now includes new hardware plugins for branch target buffering (BtbPlugin), global history-based conditional prediction (GSharePlugin), branch history tracking (HistoryPlugin), and a centralized learning aggregator (LearnPlugin). These components introduce new fetch-pipeline signals for aligned jumps and branch slices, support configurable BTB/RAS parameters, and enable the processor to learn and forget branch prediction patterns to improve execution flow accuracy.

src/main/scala/vexiiriscv/prediction · high confidence

The execute stage now includes dedicated plugins for the RISC-V Zkn AES extension (AesZknPlugin), the Zba/Zbb/Zbc/Zbs/Zbkb bit manipulation extensions (Bitmanip), and branch/jump logic (BranchPlugin). Additionally, new plugins implement barrel shifting (BarrelShifterPlugin), integer division (DivPlugin), and a RAM-backed CSR storage layer (CsrRamPlugin) to support performance counters and large CSRs. These changes expand the processor's instruction set support and refine the execution pipeline's handling of control flow and system registers.

src/main/scala/vexiiriscv/execute · high confidence

This change introduces new hardware components for the CPU core. It adds \DivRadix\ and \DivRadix2\ modules to support radix-2 and radix-4 unsigned integer division, with \DivRadix2\ offering a configurable low-area mode. It also adds \EmbeddedJtagPlugin\ to integrate the RISC-V debug infrastructure (JTAG TAP and Debug Module) directly into the CPU, simplifying SoC integration. Additionally, it includes \ImsicPlugin\ for AIA-compliant interrupt controller support, \IndirectCsrPlugin\ to simplify indirect CSR handling, and \TesterPlugin\ for simulation testing with random freezes and MMU refill injection.

src/main/scala/vexiiriscv/misc · high confidence

Added CtrlLaneApi and NodeLaneApi traits that introduce a LANE\_SEL signal and associated helper methods (isValid, isReady, isCancel, apply, insert, bypass) to support multi-lane pipeline architectures. This allows users to layer execution lanes (e.g., lane 0 and lane 1) within a single pipeline node or control link, enabling features like dual-issue and multiple branch plugins on different lanes.

src/main/scala/spinal/lib/misc/pipeline · high confidence

The instruction fetch logic has been restructured into a plugin-based architecture, introducing a FetchPipelinePlugin to manage the fetch stages and a PcPlugin to handle program counter state and jump arbitration. Two distinct fetch implementations are now available: FetchL1Plugin, a non-blocking L1 instruction cache with configurable set/way parameters, and FetchCachelessPlugin, which supports out-of-order memory responses for direct bus access. Both implementations include dedicated bridge plugins (FetchL1Bridge and FetchCachelessBridge) that allow the internal fetch bus to connect to external Tilelink, AXI4, or Wishbone interfaces, enabling flexible integration with various memory systems.

src/main/scala/vexiiriscv/fetch · high confidence

Added src/main/scala/vexiiriscv/compat/MultiportRam.scala, which provides several implementations of multi-port RAM (supporting multiple write and read ports) built on top of simple dual-port RAM primitives. The file includes asynchronous and synchronous variants using XOR-based, register-based, and mux-based techniques, along with associated command and response bundles for integration.

src/main/scala/vexiiriscv/compat · high confidence

The VexiiRiscv tester module now includes a comprehensive testbench framework. This introduces a builder class (TestArgs) for constructing simulation arguments, a main TestBench entry point supporting multi-core configurations and various bus protocols (AXI4, Wishbone, Tilelink), and a dedicated Tilelink-based testbench (TilelinkTestBench) for SoC-level verification. Additionally, a TestBenchServer is added, allowing users to start a persistent simulation server to run multiple test cases efficiently without recompilation overhead, and a Finite State Machine (Fsm) framework is provided to define directed test sequences based on terminal I/O.

src/main/scala/vexiiriscv/tester · high confidence

The register file now supports a configurable backend that can mask reads during write cycles (controlled by the \maskReadDuringWrite\ parameter). This behavioral change ensures that read data is suppressed when a concurrent write targets the same address, preventing stale or undefined values from being observed by the CPU. The implementation includes a new \RegFileMem\ component and a \RegFilePlugin\ that manages read/write port arbitration and initialization, allowing users to select between different register file topologies (e.g., RAM-based vs. register-based) while adhering to this safety mechanism.

src/main/scala/vexiiriscv/regfile · high confidence

The \vexiiriscv/schedule\ module now includes new \DispatchPlugin\, \ReschedulePlugin\, and \Service\ components that implement the core logic for collecting decoded instructions, determining execution lane eligibility based on dependencies and hazards, and issuing instructions to execution units. This change introduces a new reservation system allowing static scheduling of operations (such as floating-point) that share resources at different pipeline stages, and adds precise flush hazard tracking to prevent false positives and ensure correct pipeline behavior during speculative execution and branch mispredictions.

src/main/scala/vexiiriscv/schedule · high confidence

The decode stage has been restructured into a composable plugin architecture (AlignerPlugin, DecodePipelinePlugin, DecoderPlugin) that handles instruction deserialization, RVC decompression, and branch prediction correction. The AlignerPlugin manages fetching aligned instruction slices, supporting both buffered and direct-feed modes to optimize timing, while the DecoderPlugin integrates with the prediction system to fix broken instruction streams caused by branch target buffer (BTB) mispredictions, ensuring correct instruction decoding even when predictions are misaligned.

src/main/scala/vexiiriscv/decode · high confidence

Added IMSIC peripheral emulator and IO device manager for simulation; Added Konata simulation backend for test generation; Added MultithreadedFunSuite test base class; Added documentation examples for VexiiRiscv plugin system; Added hardware stability and synthesis benchmark test utilities; Added tests for SpinalHDL Fiber plugin synchronization patterns; Automated regression testing framework for VexiiRiscv.

The project now includes several external Git submodules in the \ext/\ directory to support RISC-V software and hardware simulation. Specifically, \NaxSoftware\, \SpinalHDL\, \riscv-isa-sim\, and \rvls\ have been added as subproject commits, providing the necessary codebases for software testing, hardware description, instruction set simulation, and low-level simulation libraries. A new \package.mill\ file was also added to define the build package structure for these extensions.

ext · high confidence

The project now uses an SBT build file (build.sbt) to manage dependencies and compilation. This configuration sets the project version to 2.0.0, defines Scala cross-compilation versions, and includes specific libraries such as ScalaTest 3.2.17, SnakeYAML 1.8, jelf 0.7.0, and jssc 2.8.0. It also supports building SpinalHDL from source via environment variables and configures JNI bindings for RISC-V simulation.

(dependencies) · high confidence

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

• First survey — no prior run to compare against. CAI 55.

• Code Health 90
• Architecture 95
• Maturity 51
• Readiness 46
• Security 60

• 300 commits — 247 feature/other, 53 fixes

• src/main — 224 commits
• (repo) — 38 commits
• src/test — 13 commits
• .github/workflows — 10 commits
• (root) — 5 commits
• ext/NaxSoftware — 5 commits
• ext/rvls — 3 commits
• ext/SpinalHDL — 1 commit
• ext/riscv-isa-sim — 1 commit

• fix: Add asid width as regression dimension
• fix: Add crypto instruction regression
• fix: Add hypervisor option to regression
• fix: Add initial multiple core support for regression test
• fix: Add multiple core support for regression test
• fix: Allow to execute regression for mill
• fix: Fix #108
• fix: Fix #129 microsoc without spiflash
• fix: Fix #156 (FPU fcvt not always checking RM is legal)
• fix: Fix --debug-jtag-tap missing privParam.withDebug (https://github.com/SpinalHDL/VexiiRiscv/issues/104)
• fix: Fix CSR remapping logic for read/write stage
• fix: Fix GVA field update method
• fix: Fix GenerateTilelink rdtime
• fix: Fix IMSIC file build
• fix: Fix IMSIC file interrupt offset calculation
• fix: Fix MMU page fault check priority in TLB refill process
• fix: Fix Mhz -> MHz in the README.md
• fix: Fix MmuPlugin effecitve privilege calculation
• fix: Fix PMP granularity check
• fix: Fix ParamSimple.hashCode() to handle withISA Set fields
• …and 280 more

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

SpinalHDL/VexiiRiscv was measured the same way every project in this corpus was: the same rubric, at a pinned commit, with the result published in full. Point a surveyor at a repository you know and see whether you agree with it.