ucb-bar/chipyard

Chipyard is an open-source hardware design framework for RISC-V processors that enables the generation, simulation, and deployment of configurable system-on-chip designs. It provides a modular infrastructure for integrating various processor cores and accelerators, supporting execution across FPGA platforms, cycle-accurate hardware emulation via FireSim, and standard RTL simulators. The system also includes tooling for full VLSI tapeout flows and bare-metal software verification.

16 changes.

This period centered on the initial release of Chipyard 1.14.0, which established a new modular project structure by removing legacy monolithic examples and bootroms. The work involved a comprehensive rewrite of build and initialization scripts, the integration of VLSI flows with Hammer, and the expansion of simulation and testing capabilities through VCS, CMake-based bare-metal suites, and torture testing. Additionally, the documentation system was migrated to Astro, and various toolchain and generator submodules were updated to support modern RISC-V development workflows.

13 changes.

This period focused on restructuring the Chipyard configuration system into modular, domain-specific files to improve maintainability and clarity. It also introduced comprehensive support for multiple FPGA boards, including the VCU118 and Arty, alongside a unified build system and advanced clocking infrastructure.

19 changes.

This period focused on expanding hardware support by adding initial configurations for multiple FPGA boards, including VC707, ZCU104, Arty100T, Nexys Video, and Intel Datastorm. It also introduced significant simulation capabilities through the FireChip generator for FireSim integration, Xcelium simulator support, and SpikeTile C++ simulation. Additionally, the codebase underwent architectural improvements with modular harness binders, configurable I/O mapping, and Chisel 6-based generation stages.

4 changes.

This period focused on expanding hardware compatibility by adding initial support for the Genesys 2 and ZCU104 FPGA boards, including necessary configuration and harness files. Concurrently, the project introduced experimental support for Chisel 7 and CIRCT, replacing the previous FIRRTL-based flow with a new generation pipeline. These changes were accompanied by routine updates to the Zephyr RTOS submodule.

New example modules have been added to the Chipyard DspTools generator to demonstrate how to integrate DSP blocks into a system. This includes \WriteQueue\ and \ReadQueue\ for memory-mapped data streaming, a \GenericFIR\ filter implementation using direct-form cells, and a \StreamingPassthrough\ module for sanity checking. These components are wired as TileLink chains with AXI4Stream interfaces and configurable CSR addresses, allowing users to easily prototype and test DSP functionality within their Chipyard designs.

generators/chipyard/src/main/scala/example/dsptools · high confidence

A new Tcl script (run\_impl\_bitstream.tcl) has been added to the FPGA scripts directory to automate the post-synthesis implementation flow. This script accepts a synthesis checkpoint, board configuration, and output directory as arguments, then executes the design optimization, placement, and routing stages. It generates the final bitstream file along with comprehensive reports covering timing, DRC, CDC, clock utilization, and design analysis, ensuring a complete and verified bitstream output for the target FPGA.

fpga/scripts · high confidence

This change introduces a new tutorial directory containing a build script and configuration files for running Gemmini RoCC tests. The build script compiles and copies ResNet50 and MobileNet models for both bare-metal and Linux environments. Configuration files are provided for these models, specifying base configurations, host initialization steps, binary paths, and Spike emulator arguments with the Gemmini extension enabled.

software/tutorial · high confidence

This change introduces the C++ source files for SpikeTile, a new component that integrates the Spike RISC-V simulator with Chipyard. The implementation provides a simulation interface (spiketile.cc) that manages processor state, instruction and data caches, and a Tightly Coupled Memory (TCM) region. It supports both DTM-based and TSI-based host-target simulation interfaces, allowing users to run RISC-V software on a simulated tile with configurable cache parameters and memory regions.

generators/chipyard/src/main/resources/csrc · high confidence

This update adds the \spiketile.v\ module, enabling the use of SpikeTile (a Spike-based tile) within Chipyard designs, including support for TightlyCoupledMemory and correct reset handling. It also introduces new Verilog source files: \Analog.v\ for analog constants, \ClockDividerN.sv\ for unsynthesizable clock division with improved edge timing, and \GCDMMIOBlackBox.v\ for a GCD MMIO black box.

generators/chipyard/src/main/resources/vsrc · high confidence

Introduces a new SD card boot loader for the VCU118 FPGA, including the source code (C and assembly), build system (Makefile), linker scripts, and platform definitions. This enables the FPGA to load a payload from an SD card via SPI, supporting payloads up to 30 MiB at a 25 MHz SPI clock speed, and provides the necessary low-level drivers and hardware abstraction for UART, GPIO, SPI, and interrupt controllers.

fpga/src/main/resources/vcu118 · high confidence

This change introduces support for the Cadence Xcelium simulator, allowing users to run simulations using the xrun binary. The implementation includes a dedicated Makefile and shared rules (xcelium.mk) that configure compilation flags, random seed handling, and preprocessor defines specific to Xcelium. It also provides an argument reshuffling wrapper to translate standard simulator arguments (such as VCD file paths) into Xcelium-specific formats and handles library linking via LD\_PRELOAD to resolve potential libstdc++ conflicts.

sims/xcelium · high confidence

This change introduces a new build system for the embench-iot benchmark suite within the software/embench directory. It includes a build script that compiles the benchmarks for the RISC-V architecture (using the riscv32 target with a riscv64 compiler) and a .gitignore file to exclude the resulting build artifacts. The embench-iot source is included as a git submodule, and the build process copies the resulting binary benchmarks into a dedicated build directory.

software/embench · high confidence

This change introduces the first hardware platform support for the Digilent Nexys Video FPGA board. It adds configuration classes (Configs.scala) that define system parameters such as 512MB external memory, 50MHz clock frequencies, and UART-based TSI communication, alongside Harness.scala and HarnessBinders.scala which wire up the UART, DDR, and GPIO interfaces to the chip. Users can now build and deploy Chipyard designs specifically targeting the Nexys Video hardware.

fpga/src/main/scala/nexysvideo · high confidence

Introduces configuration, harness binders, and test harness files for the Xilinx ZCU104 FPGA board. This enables users to build and run designs on ZCU104 hardware, including support for UART, SPI/SDIO, DDR memory, and JTAG interfaces, with specific configurations for Rocket and Boom processors.

fpga/src/main/scala/zcu104 · high confidence

This change introduces the initial hardware support configuration for the Xilinx VC707 FPGA board. It adds specific Chisel configuration classes (Configs.scala) that define peripheral mappings for UART, SPI (SD card), and DDR memory, along with harness binders (HarnessBinders.scala) to connect these peripherals to the FPGA's physical I/O. The TestHarness.scala file implements the top-level FPGA wrapper, handling clock generation via the board's PLL, reset logic, and the integration of the chipyard design with the VC707 shell infrastructure.

fpga/src/main/scala/vc707 · high confidence

This change introduces a new trace generation generator (tracegen) located in generators/tracegen, enabling users to generate and verify instruction traces for Rocket Chip and BOOM (v3 and v4) processor configurations. The addition includes configuration classes (Configs.scala) to attach TraceGen tiles to the subsystem, a system definition (System.scala) that integrates these tiles and exposes status signals, and a Makefile (tracegen.mk) to automate simulation and trace checking via the AXE tool. This allows developers to validate processor microarchitecture behavior against expected instruction sequences.

generators/tracegen · high confidence

The generators/chipyard/src/main/resources/hls directory now contains the source files for a High-Level Synthesis (HLS) Greatest Common Divisor (GCD) accelerator example. This includes the C++ implementation (HLSAccel.cpp), a Makefile to orchestrate the Vitis HLS build process, and the corresponding TCL script (run\_hls.tcl) configured for a specific FPGA part (xcu200) and clock period. These files provide a reference implementation for generating GCD logic via HLS within the Chipyard environment.

generators/chipyard/src/main/resources/hls · high confidence

This change introduces a new feature in the Chipyard generator that automatically generates Unified Power Format (UPF) files for power-aware design. The new files in \generators/chipyard/src/main/scala/upf\ implement a system to traverse the design's LazyModule hierarchy, define power domains based on configurable inputs (voltage levels, gating, hierarchy), and output standard UPF commands including power switches, supply nets, and power state tables. This allows users to define power domains via \UPFInputs.scala\ and have the corresponding UPF artifacts generated during the build process.

generators/chipyard/src/main/scala/upf · high confidence

The iocell module now includes new Scala definitions for modeling hardware I/O cells, providing generic implementations for analog, digital input, digital output, and GPIO scenarios. These changes introduce base bundle types (AnalogIOCellBundle, DigitalGPIOCellBundle, etc.) and corresponding black-box wrappers with inline Verilog models, allowing users to create wrapper modules for foundry-specific cells. Additionally, an AnalogConst black box is added to model constant analog values, supporting the integration of analog signals within the Chisel design flow.

generators/chipyard/src/main/scala/iocell · high confidence

The software directory now includes several new Git submodules, providing direct access to specific toolchains and workload sets. Users can now utilize the Bare-Metal IDE for development, run the CoreMark benchmark, and access specific workload collections including FireSim paper workloads, NVDLA workloads, and SPEC 2017/2026 benchmarks. Additionally, the Tacit decoder submodule has been added to support related hardware/software co-verification.

software · high confidence

The FPGA resource configuration now includes support for the VC707 and ZCU104 boards. Both board-specific resource directories have been added as symbolic links pointing to the existing VCU118 configuration, effectively replicating the VCU118 setup for these new platforms.

fpga/src/main/resources · high confidence

The tools directory now includes a new 'torture' submodule and a corresponding 'torture.mk' makefile. This adds two new build targets, 'torture' and 'torture-overnight', allowing users to run automated stress tests against the RTL testbench. The overnight target supports passing custom test options via the TORTURE\_ONIGHT\_OPTIONS variable.

tools · high confidence

The Arty FPGA platform is now supported through a new harness-based architecture. This change introduces HarnessBinders and IOBinders to explicitly map JTAG, UART, and debug reset signals to the Arty board's physical pins, replacing previous implicit wiring. It also adds configuration classes (Configs.scala) to set bus frequencies and clock sources, and a TestHarness that instantiates the ChipTop using the ArtyShell infrastructure.

fpga/src/main/scala/arty · high confidence

This change introduces a new \tools/stage-chisel7\ module that provides an experimental backend for generating hardware using Chisel 7 and CIRCT. It replaces the previous FIRRTL-based flow with a new \ChipyardStage\ and \ChipyardChiselStage\ that leverage the Chisel 7 phase manager to handle elaboration, annotation processing, and artifact generation (including FIRRTL annotations, test suite makefrags, and elaboration artifacts) directly through the CIRCT pipeline. Users can now opt into this experimental path to generate designs using the newer Chisel/CIRCT toolchain.

tools/stage-chisel7 · high confidence

Adds initial hardware support for the Arty100T FPGA board, including configuration files, harness logic, and pin mappings. The platform supports TSI-over-UART communication via the on-board USB-UART or PMOD JD pins, JTAG debugging via dedicated pins, and DDR memory access. A bringup configuration is also provided that uses PMOD GPIOs for Serial-TL communication.

fpga/src/main/scala/arty100t · high confidence

Adds the initial configuration and hardware description for the Xilinx VCU118 FPGA board, enabling users to build and run Chipyard designs on this specific hardware. The change introduces configuration classes (RocketVCU118Config, BoomVCU118Config) that set up the system bus frequencies, DDR memory size (2GB), and peripheral mappings for UART, SPI (SDIO), and JTAG debug interfaces. It also includes the TestHarness implementation, custom overlays for clock generation and DDR memory interface (MIG), and harness binders to connect the internal design to the physical FPGA I/O pins.

fpga/src/main/scala/vcu118 · high confidence

The vlsi directory now provides a complete Makefile-based build system for VLSI flows, integrating with the Hammer toolchain. This includes example configuration files for ASAP7, Sky130, and OpenROAD technologies, along with Python drivers for custom placement and routing hooks. The setup supports simulation, synthesis, and power analysis targets, enabling users to run end-to-end VLSI flows for designs like TinyRocket.

vlsi · high confidence

The generators directory is now populated with a comprehensive set of submodules for core components and accelerators, including rocket-chip, BOOM, CVA6, Ibex, Gemmini, Radiance, NVDLA, Ara, Tacit, and others. Additionally, a new unit test infrastructure has been added under generators/chipyard, introducing a TestHarness and UnitTestSuite module to facilitate automated verification of generated designs.

generators · high confidence

This entry marks the initial release of Chipyard 1.14.0, establishing the project's foundational structure and configuration. It introduces a new changelog following the Keep a Changelog format, updates the documentation build system to use Starlight and Astro on ReadTheDocs, and configures automated backporting via Mergify. The release also adds support for AWS F2 in FireSim, limited Chisel 7 compatibility, Zephyr RTOS, and various new RTL examples including async reset and I2C peripherals.

(repo-wide) · high confidence

Adds configuration and harness files for the Genesys 2 FPGA board, enabling users to build and run designs on this hardware. The changes include \Configs.scala\ with specific settings for the Genesys 2 (such as 1GB DDR memory, UART-TSI communication, and uniform bus frequencies), \Harness.scala\ for clocking and LED status indication, and \HarnessBinders.scala\ to map UART, DDR, and SerialTL interfaces to the board's physical pins.

fpga/src/main/scala/genesys2 · high confidence

Adds configuration and harness files to enable running the system on the Intel Datastorm FPGA board. This includes specific hardware bindings for DDR memory, UART (including PMOD and TSI variants), JTAG, and SerialTL-to-FMC interfaces, along with system configurations tailored for the board's constraints (e.g., 1GB memory, single big core).

fpga/src/main/scala/datastorm · high confidence

The generator now provides a new \ChipTop\ entry point that instantiates a \DigitalTop\ system, exposing configurable periphery devices (UART, I2C, PWM, SPI, GPIO, etc.) and supporting both Rocket and BOOM cores via a unified \DigitalTop\ trait composition. A new \ConfigFinder\ utility allows users to programmatically discover and list valid Chipyard configuration classes suitable for build targets, filtering out internal or example-specific configs. Additionally, a \SpikeTile\ implementation is added to enable software simulation and co-simulation using the Spike emulator, integrating with the existing diplomatic clock and reset infrastructure.

generators/chipyard/src/main/scala · high confidence

This change adds the FireChip generator module, providing the core infrastructure to generate and simulate designs using FireSim. It introduces the \FireSim\ top-level harness module, which instantiates clock and reset bridges, and a comprehensive set of \BridgeBinders\ that map target peripherals (such as FASED memory, NIC, UART, and block devices) to FireSim simulation bridges. The update includes a new C++ simulation driver (\firesim\_top.cc\) that manages the simulation loop and profiling, along with a suite of Makefiles (\build.mk\, \driver.mk\, \metasim.mk\) that configure the build process for Verilator, VCS, and Xcelium backends. Additionally, it provides Scala configuration presets (\TargetConfigs.scala\) for various target designs (Rocket, Boom, CVA6) and platforms (AWS F1, F2, Xilinx Alveo), and establishes a test suite (\FireSimTestSuite.scala\) to validate these configurations.

generators/firechip/chip · high confidence

The test harness has been restructured into a modular system within the \chipyard.harness\ package. This introduces a \HarnessBinder\ configuration pattern that allows users to selectively connect simulation models (such as \SimDRAM\, \SimAXIMem\, \SimJTAG\, \UARTAdapter\, and \SimNetwork\) to specific ChipTop ports via declarative configs. It also adds a \HarnessClockInstantiator\ trait with an \AbsoluteFreqHarnessClockInstantiator\ implementation, enabling precise, Verilog-based clock generation for simulation rather than relying on implicit harness clocks. Additionally, a \MultiHarnessBinder\ API is provided to support multi-chip configurations by connecting ports across different chiplets.

generators/chipyard/src/main/scala/harness · high confidence

This change adds a suite of new Scala source files in the \generators/firechip/goldengateimplementations\ directory, introducing concrete Golden Gate bridge modules for various hardware interfaces. Specifically, it adds \BlockDevBridgeModule\ for block device simulation with configurable read/write latency pipes, \CTCBridgeModule\ for cycle-accurate CTC (Cycle-Counting Timer) bridge support with token batching, \CospikeBridgeModule\ for instruction tracing via Cospike, \DMIBridgeModule\ for Debug Module Interface access, \GroundTestBridgeModule\ for basic connectivity testing, \SimpleNICBridgeModule\ for network interface simulation with token bundling, \TSIBridgeModule\ for TSI (Target System Interface) communication, \TracerVBridgeModule\ for advanced instruction tracing with PC and cycle-count triggers, and \UARTBridgeModule\ for UART serial port simulation. These files establish the host-side hardware models required for these peripherals to interact with the FireSim simulation driver.

generators/firechip/goldengateimplementations · high confidence

This change introduces the target-side Chisel interface definitions and the corresponding host-side C++ bridge drivers for several key simulation components. The new files in \bridgeinterfaces\ define the hardware contracts for Block Device, CTC (Chip-to-Chip), Cospike (co-simulation with Spike), DMI (Debug Module Interface), Ground Test, SimpleNIC, TSI (Target-Side Interface), TileTrace, TracerV, and UART bridges. Correspondingly, the \bridgestubs\ directory adds the C++ implementations that run on the host to manage these bridges, including memory pooling and thread-pooling utilities for Cospike trace processing, latency-configurable block device emulation, and FIFO-based inter-chip communication for CTC. This establishes the foundational communication layer between the simulated FPGA design and the host-side simulation infrastructure.

generators/firechip/bridgestubs · high confidence

Added new example files in the \chipyard.example\ package to demonstrate advanced integration patterns. \CustomChipTop.scala\ and \EmptyChipTop.scala\ show how to override the top-level module and IOCell definitions to support custom I/O cells and minimal topologies. \FlatChipTop.scala\ and \FlatTestHarness.scala\ provide a 'flat' architecture that bypasses IOBinders, requiring explicit construction of all ports (clock, reset, JTAG, UART, SerialTL) and manual wiring of the test harness, offering a lower-level alternative to the standard binder-based approach.

generators/chipyard/src/main/scala/example · high confidence

The tapeout tooling now includes a comprehensive macro library and compiler framework. This adds support for parsing and generating SRAM, filler, flip-chip, and IO macros from JSON configurations, enabling the macro compiler to map design memories to library macros using configurable cost metrics and multiple compilation modes (such as strict, synflops, and fallback).

tools/tapeout · high confidence

The VCS simulator is now supported for RTL simulation, allowing users to generate and run simulations using Synopsys VCS. This change introduces build rules for both standard and debug modes, with support for generating waveform files in either FSDB or VPD format (controlled by the USE\_VPD variable). It also adds support for setting a random seed for simulation initialization via the RANDOM\_SEED variable, and ensures that simulator output is correctly piped to avoid stdout interference.

sims/vcs · high confidence

The bootrom source code (bootrom.S), its build script (Makefile), and associated gitignore rules have been deleted from the repository. This removes the standalone assembly-based bootloader that previously waited for serial interrupts and handled basic trap setup, indicating this component is no longer maintained or used in this location.

bootrom · high confidence

The \Configs.scala\, \TestHarness.scala\, and \Top.scala\ files in the \src/main\ directory have been removed. This deletes the previous \ExampleTop\ implementation, its associated Chisel module/bundle definitions, and the default configuration hierarchy that wired together peripherals like the serial adapter, boot ROM, and memory controller. Users relying on this specific monolithic example setup will no longer have access to these files, consistent with the project's move to separate PWM and basic examples into distinct packages.

src/main · high confidence

The monolithic ConfigFragments.scala file has been split into six distinct files—ClockingFragments, PeripheralFragments, RoCCFragments, SubsystemFragments, TileFragments, and TracegenFragments—to improve organization and maintainability. This change restructures the codebase by grouping configuration mixins according to their functional domain (e.g., clocking, peripherals, RoCC accelerators, subsystem parameters, tile settings, and trace generation) without altering the available configuration options or their behavior.

generators/chipyard/src/main/scala/config/fragments · high confidence

The repository now supports a \.ciignore\ file to define patterns for directories or files that should not trigger CI builds. When a commit only affects paths matching these patterns, a pre-commit hook automatically prefixes the commit message with \\[skip ci\]\, preventing unnecessary CI execution. This allows developers to make changes to documentation or other ignored areas without incurring CI costs.

.githooks · high confidence

The clocking subsystem in generators/chipyard/src/main/scala/clocking has been completely rewritten to support advanced clock management and improve simulator compatibility. This change introduces a new diplomatic clock graph architecture, including \CanHaveClockTap\ for exposing clock signals and \ClockBinders\ that define how clocks are generated and connected (supporting PLL selector dividers, passthrough modes, and single-clock broadcasting). It adds TileLink-controlled hardware blocks (\TLClockDivider\, \TLClockSelector\, \TileClockGater\, \TileResetSetter\) that allow software to dynamically manage clock frequencies, select clock sources, and control tile-level power/clock states. The update also introduces \HasChipyardPRCI\ to centralize PRCI configuration, adds support for asynchronous resets via \ClockGroupAsyncResetCoercer\, and includes a \DividerOnlyClockGenerator\ with frequency selection logic to replace the previous \IdealizedPll\. These changes collectively modernize the clocking API, improve hierarchical physical design support, and fix synchronization issues in RTL simulators like Verilator.

generators/chipyard/src/main/scala/clocking · high confidence

The repository setup workflow has been significantly restructured to improve reliability, speed, and modularity. The main entry point, build-setup.sh, now orchestrates a step-by-step installation process (conda, submodules, toolchains, pre-compilation, FireSim, FireMarshal, CIRCT) with granular skip flags and support for a leaner conda environment. Submodule initialization has been split into dedicated scripts (init-submodules-no-riscv-tools.sh) that support shallow cloning, selective feature enablement (e.g., Gemmini, NVDLA), and better error handling. Toolchain building is now modularized via build-toolchain-extra.sh and build-util.sh, allowing for cleaner builds of Spike, libgloss, and tests. New scripts handle specific tasks like generating loadarch checkpoints (generate-ckpt.sh), verifying tracegen outputs (check-tracegen.sh), and managing CIRCT builds from source (build-circt-from-source.sh). Python utilities have been updated to Python 3 (insert-includes.py, replace-content.py) and enhanced for better Verilog processing (uniquify-module-names.py, split-mems-conf.py).

scripts · high confidence

The Chipyard generator now uses a new IOBinders system to map internal subsystem traits to specific top-level IO cells and ports. This change replaces the previous monolithic IO binding approach with a composable, trait-based mechanism that allows harnesses to dynamically connect peripherals (such as GPIO, UART, SPI, and AXI ports) to external IO cells based on the target system's configuration. Users can now override or compose custom IO binding behaviors for specific system traits, enabling more flexible integration of test harnesses and custom peripherals without modifying core generator code.

generators/chipyard/src/main/scala/iobinders · high confidence

The \tools/stage\ module now provides a complete generation pipeline built on Chisel 6 and CIRCT, replacing the previous implementation. This change introduces a new \ChipyardStage\ and \ChipyardChiselStage\ that manage the compilation flow via a defined phase manager, including specific phases for configuration checks, pre-elaboration, FIRRTL annotation generation, and test suite makefrag creation. Users benefit from updated command-line options (such as \--legacy-configs\ and \--emit-legacy-sfc\) and the ability to optionally generate legacy FIRRTL2 SFC output, aligning the toolchain with modern Chisel 6 standards.

tools/stage · high confidence

The FPGA build process has been replaced with a new Makefile-based system that supports a wide range of boards including VCU118, VC707, ZCU104, Genesys 2, Nexys Video, Arty 35T/100T, and Intel Datastorm. This change introduces a unified build flow using Chisel 6 (enforced via USE\_CHISEL6=1) and integrates the fpga-shells submodule for hardware abstraction, allowing users to select their target board via the SUB\_PROJECT variable and generate bitstreams or Verilog sources consistently across different FPGA platforms.

fpga · high confidence

The configuration system has been restructured to improve modularity and clarity. A new \AbstractConfig\ serves as the central base configuration, defining default harness binders, IO binders, memory systems, and clocking settings. Specific processor configurations are now split into dedicated files: \BoomConfigs.scala\ for BOOM V3 and V4 variants, \ChipConfigs.scala\ for chip-level and bringup prototypes (like \ChipLikeRocketConfig\), \ChipletConfigs.scala\ for multi-chiplet communication examples, \ClockingConfigs.scala\ for clock generation strategies, \HeteroConfigs.scala\ for mixed Rocket/BOOM systems, \MMIOAcceleratorConfigs.scala\ for accelerator examples, \MemorySystemConfigs.scala\ for memory topology variations, \NoCConfigs.scala\ for Network-on-Chip topologies, \NoCoreConfigs.scala\ for core-less test configurations, and \PeripheralDeviceConfigs.scala\ for peripheral device additions. This separation allows users to easily compose and understand specific system aspects without navigating a monolithic config file.

generators/chipyard/src/main/scala/config · high confidence

The simulation build system now uses a centralized configuration file (common-sim-flags.mk) to define common compiler and linker flags, enforcing C++17 standard compliance and optimizing for performance. This change also updates the FireSim submodule to a specific commit, ensuring compatibility with the new build configuration and potentially bringing in upstream improvements or fixes.

sims · high confidence

The RISC-V toolchain components have been updated to newer versions: riscv-isa-sim, riscv-openocd, riscv-pk, riscv-spike-devices, and riscv-tests. These updates ensure the simulation environment and development tools are aligned with the latest upstream changes, potentially improving compatibility and fixing known issues in the toolchain stack.

toolchains/riscv-tools · high confidence

The libgloss submodule within the toolchains directory has been updated to a new commit (177ce07). This change incorporates fixes and support for trap handlers, ensuring that the RISC-V toolchain correctly handles these low-level exceptions during execution.

toolchains · high confidence

The Zephyr RTOS submodule has been updated to commit cd45a528d3bf81f9c7aa2a63f9fe512eee0881b0. This change incorporates upstream Zephyr updates, which may include bug fixes, new features, or API changes from the Zephyr project.

software/zephyrproject · medium confidence

Added tests for PLL reference clock selection; New CMake-based test suite for bare-metal verification.

The documentation build system has migrated from Sphinx to Astro with the Starlight theme. This change introduces new Node.js dependencies (\astro\ ^7.1.3, \@astrojs/starlight\ 0.41.3, and \chokidar\ 5.0.0) and updates the build scripts to use Astro for development and generation, replacing the previous Python-based Sphinx tooling.

(dependencies) · high confidence

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

• First survey — no prior run to compare against. CAI 70.

• Code Health 88
• Architecture 95
• Maturity 64
• Readiness 76
• Security 68

• 300 commits — 249 feature/other, 51 fixes

• (repo) — 110 commits
• generators/chipyard — 31 commits
• (root) — 25 commits
• .github/scripts — 10 commits
• generators/firechip — 10 commits
• sims/vcs — 10 commits
• conda-reqs/conda-lock-reqs — 9 commits
• docs/Software — 7 commits
• generators/radiance — 6 commits
• generators/testchipip — 6 commits
• docs/Generators — 5 commits
• generators/boom — 5 commits
• scripts/init-submodules-no-riscv-tools-nolog.sh — 5 commits
• sims/firesim — 5 commits
• toolchains/riscv-tools — 5 commits
• .github/workflows — 4 commits
• fpga/src — 4 commits
• generators/gemmini — 4 commits
• generators/rocket-chip — 4 commits
• conda-reqs/chipyard-extended.yaml — 3 commits

• fix: Bump testchipip for the cosim fixes
• fix: Bump vector components to fix whole-register vill
• fix: Fix CI
• fix: Fix WithRadBootROM path, use full import paths
• fix: Fix ctc bridge to be cycle-accurate
• fix: Fix ctc harness binders for no phy
• fix: Fix link in CTC docs
• fix: Fix support for non-gnu SED
• fix: Fix the spec2026 submodule: https URL and skip it in the default init, like spec2017
• fix: Fix: reference link syntax
• fix: Merge branch 'main' into glibc-fix
• fix: Merge branch 'main' into glibc-fix
• fix: Merge pull request #2193 from ucb-bar/ci-doc-fix
• fix: Merge pull request #2262 from tymcauley/testchipip-fix-xcelium
• fix: Merge pull request #2271 from marie-anne-xu/glibc-fix
• fix: Merge pull request #2283 from ucb-bar/fix-ci
• fix: Merge pull request #2288 from ucb-bar/fix-insert-includes-script
• fix: Merge pull request #2349 from nour-jamjoom5/graphml-fix
• fix: Patch: Docs Dev Env Fix (#2363)
• fix: Remove no-dont-touch hack - this bug has been fixed in newer CIRCT
• …and 280 more

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

ucb-bar/chipyard was measured the same way every project in this corpus was: the same rubric, at a pinned commit, with the result published in full. Point a surveyor at a repository you know and see whether you agree with it.