ucb-bar/constellation

Constellation is a Chisel-based framework for generating Network-on-Chip (NoC) hardware for heterogeneous SoCs. It provides configurable physical topologies, protocol adapters for TileLink and AXI4, and a router subsystem with flexible virtual channel allocation and routing policies. The system includes built-in traffic evaluation, latency tracking, and visualization tools to verify network performance and structure.

7 changes.

This period marks the initial release of Constellation, a Chisel-based NoC RTL generator framework, replacing the previous AstroNoC implementation. The work established the core project structure, build configuration, and a complete router subsystem with configurable topologies and protocol adapters for TileLink and AXI4. Comprehensive test suites were also added to verify the new network-on-chip designs across various configurations.

9 changes.

This period focused on building the core Network-on-Chip (NoC) infrastructure, including the foundational NoC module, channel definitions, and configurable router logic with virtual channel allocation. It also established protocol translation via TileLink adapters and integrated the NoC into system buses, while adding comprehensive test harnesses and visualization tools for validation and analysis.

Introduced a new \TopologyPlotters\ module that provides concrete implementations for visualizing various network topologies. This includes plotters for linear, 1D torus, butterfly, 2D mesh, and bidirectional tree structures, as well as a specialized plotter for terminal router topologies that composites base topology layouts with terminal node positioning. These components enable users to generate coordinate-based visual representations of their network designs.

src/main/scala/topology · high confidence

This change introduces the core \NoC\ module in \src/main/scala/noc/NoC.scala\, establishing the foundational network-on-chip infrastructure. The module supports configurable physical topologies (including hierarchical and unidirectional line structures) and allows for channel width adapters between routers to handle varying payload bits. It includes support for ingress/egress narrowing, optional router control interfaces (\RouterCtrlBundle\), and debug stall counters. The implementation generates elaboration artifacts such as GraphML and adjacency list files for visualization and verification, while also handling clock domain management for individual routers.

src/main/scala/noc · high confidence

The project is introduced as Constellation, a Chisel-based NoC RTL generator framework for heterogeneous SoCs. This initial release establishes the project structure, including a BSD 3-Clause license, Read the Docs configuration, and a .gitignore file. It also integrates external dependencies via Git submodules for the Netrace simulator and the Espresso logic minimizer, while the README provides an overview of features such as wormhole routing, arbitrary topology support, and integration with Chipyard/RocketChip.

(repo-wide) · high confidence

Adds a new Network-on-Chip (NoC) infrastructure including configurable physical topologies (e.g., 2D Mesh, Torus, Butterfly), diplomatic channel and router implementations, and protocol adapters for TileLink and AXI4. This enables users to define custom network topologies, specify flows between ingress and egress points, and connect existing TileLink or AXI4 masters/slaves to the NoC via dedicated adapter modules that handle flit serialization and routing.

repository · high confidence

Adds the core channel package for the constellation NoC, defining flit structures (BaseFlit, IngressFlit, EgressFlit) and channel bundles (Channel, IngressChannel, EgressChannel) to handle data payloads and virtual channel credits. Includes a ChannelBuffer for flow control via shift registers, a NoCMonitor for validating head/tail sequencing and flow constraints, and WidthWidget components that automatically split or merge flit payloads to support width adapters between routers with different data path sizes.

src/main/scala/channel · high confidence

Adds a complete router implementation for the NoC, including a RouterControlUnit for managing epoch cycles and per-input rate limiting, IngressUnit and EgressUnit for handling flit entry and exit with virtual network support, InputUnit and OutputUnit for buffering and credit management, and Switch/SwitchAllocator components for internal packet routing. The RouteComputer uses truth tables to determine output virtual channel selections based on flow identifiers, while the InputBuffer supports both unified and per-VC queue configurations.

src/main/scala/router · high confidence

Added \TilelinkAdapters.scala\ containing abstract and concrete modules (\TLChannelToNoC\, \TLChannelFromNoC\, and specific adapters like \TLAToNoC\, \TLBFromNoC\, etc.) that translate between TileLink channels and the internal Network-on-Chip (NoC) flit format. These modules handle address decoding, source/sink ID mapping, and payload assembly/disassembly to enable communication between TileLink devices and the NoC infrastructure.

src/main/scala/protocol · high confidence

The router's virtual channel allocator now supports multiple allocation strategies, including a new prioritizing allocator that respects flow-specific priority levels, alongside existing ISLIP, PIM (random), and single-cycle variants. This change restructures the allocator into distinct implementations (SingleVCAllocator, MultiVCAllocator) and policy traits (ISLIP, PIM, Prioritizing), allowing users to select different arbitration behaviors for input and output channels to better suit their traffic patterns.

src/main/scala/router/vcalloc · high confidence

This change introduces a new traffic evaluation system (TrafficEval) that integrates with the simulation via DPI-C interfaces in Verilog. The C++ implementation now supports generating traffic using netrace traces (controlled by a new \netrace\_enable\ parameter) in addition to the existing random traffic generation. The evaluation logic has been enhanced to track and report latency metrics, including median and maximum latency per flow and overall, as well as a latency histogram. Furthermore, the system now validates that the measured throughput and median latency meet configured requirements, reporting errors if they fall below the specified thresholds.

src/main/resources · high confidence

Added three new scripts to the repository: \increment-config-nums.py\ to automate incrementing test configuration numbers in Scala files, \install-espresso.sh\ to build and install the Espresso logic minimizer tool, and \vis.py\ to visualize NoC (Network-on-Chip) debug data using NetworkX and Matplotlib, including support for animated trace playback.

scripts · high confidence

The \astronoc\ package and its associated network-on-chip (NoC) hardware modules have been removed from the codebase. This deletion eliminates the previous implementation of the router, including the InputUnit, OutputUnit, SwitchAllocator, VCAllocator, and RouteComputer components, as well as the Flit data structure and configuration parameters. Users relying on this specific NoC architecture will no longer have access to these modules.

src/main/scala · high confidence

Users can now configure the System, Memory, Control, and Peripheral buses to integrate with the TileLink NoC via new configuration classes (WithSbusNoC, WithMbusNoC, WithCbusNoC, WithPbusNoC). These configs allow specifying TLNoC parameters and an option to inline NoC routers directly into the grouped TileLink buses, providing flexibility in how the network-on-chip is mapped to the subsystem's internal bus topology.

src/main/scala/soc · high confidence

The \src/main/scala/routing\ area now uses a new \RoutingRelation\ abstract class to define routing and channel allocation policies, replacing previous ad-hoc implementations. This change introduces a structured API where routing decisions are made via a \rel\ function that determines if a packet can proceed to a next channel, along with support for escape channels to ensure deadlock freedom. The diff adds specific routing implementations including \UnidirectionalTorus1DDatelineRouting\, \BidirectionalTorus1DDatelineRouting\, and \BidirectionalTorus1DShortestRouting\, as well as a composite \EscapeChannelRouting\ strategy that combines normal and escape channel relations. This refactoring centralizes routing logic, allowing for more flexible and verifiable routing configurations across different network topologies.

src/main/scala/routing · high confidence

Added NoC test harnesses and test suites for Chisel verification; Added test harnesses and configurations for NoC validation.

The project now uses an SBT build file (build.sbt) to manage dependencies and build settings. In standalone mode (enabled via the CONSTELLATION\_STANDALONE environment variable), it pulls in Rocket Chip 1.6.0, CDE 1.6.0, rocket-macros 1.6.0, and ChiselTest 0.5.4, along with the Chisel 3.5.6 compiler plugin. It also configures Scala 2.13.10, enables specific compiler flags, and sets up parallel test execution with a limit of 72 forked test groups.

(dependencies) · high confidence

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

• First survey — no prior run to compare against. CAI 60.

• Code Health 91
• Architecture 94
• Maturity 49
• Readiness 50
• Security 86

• 300 commits — 249 feature/other, 51 fixes

• src/main — 225 commits
• (root) — 23 commits
• (repo) — 18 commits
• .github/workflows — 11 commits
• docs/source — 11 commits
• scripts/vis.py — 7 commits
• src/test — 4 commits
• scripts/increment-config-nums.py — 1 commit

• fix: Attempt to fix CI machine using wrong cmake'
• fix: Fix :<> syntax
• fix: Fix AXI4 connect syntax
• fix: Fix AXI4-to-TL over TL-NoC
• fix: Fix CI tests
• fix: Fix Decode in Prioritizing vcalloc arb
• fix: Fix EvalConfigs 4/5
• fix: Fix EvalHarness verilator chiseltest
• fix: Fix EvalTest02
• fix: Fix IngressUnits with no flows
• fix: Fix NoC println statement
• fix: Fix OH mux in switch
• fix: Fix SharedNonblockingViftualSubnetworksRouting
• fix: Fix SwitchAllocator LRU-ish behavior
• fix: Fix TL NoC egress id computation
• fix: Fix TerminalPlane configs
• fix: Fix TerminalPlane topo to be bidirectional
• fix: Fix TestConfig60
• fix: Fix TileLink protocol node name generation
• fix: Fix VirtualNetworkWithBlocking routing rel
• …and 280 more

• 0 containers · 1 bounded contexts · 0 dependency edges (baseline)

Written by watchdog.canine.dev from the codebase's own history, inside the signed delivery this page is composed from.

ucb-bar/constellation was measured the same way every project in this corpus was: the same rubric, at a pinned commit, with the result published in full. Point a surveyor at a repository you know and see whether you agree with it.